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Type of computer hardware interrupt

Message Signaled Interrupts (MSI) are a method of signaling interrupts, using special in band messages to replace traditional out of band signals on dedicated interrupt lines. While message signaled interrupts are more complex to implement in a device, they have some significant advantages over pin based out of band interrupt signalling, such as improved interrupt handling performance. This is in contrast to traditional interrupt mechanisms, such as the legacy interrupt request (IRQ) system. Message signaled interrupts are supported in PCI bus since its version 2.2, and in later available PCI Express bus. Some non PCI architectures also use message signaled interrupts.

Traditionally, a device has an interrupt line (pin) which it asserts when it wants to signal an interrupt to the host processing environment. This traditional form of interrupt signalling is an out of band form of control signalling since it uses a dedicated path to send such control information, separately from the main data path. MSI replaces those dedicated interrupt lines with in band signalling, by exchanging special messages that indicate interrupts through the main data path. In particular, MSI allows the device to write a small amount of interrupt describing data to a special memory mapped I/O address, and the chipset then delivers the corresponding interrupt to a processor. A common misconception with MSI is that it allows the device to send data to a processor as part of the interrupt. The data that is sent as part of the memory write transaction is used by the chipset to determine which interrupt to trigger on which processor; that data is not available for the device to communicate additional information to the interrupt handler.

While more complex to implement in a device, message signalled interrupts have some significant advantages over pin based out of band interrupt signalling. On the mechanical side, fewer pins makes for a simpler, cheaper, and more reliable connector. While this is no advantage to the standard PCI connector, PCI Express takes advantage of these savings. MSI increases the number of interrupts that are possible. While conventional PCI was limited to four interrupts per card (and,
because they were shared among all cards, most are using only one), message signalled interrupts allow dozens of interrupts per card, when that is useful. To prevent this race, interrupt handlers were required to read from the device to ensure that the DMA write had finished. This read had a moderate performance penalty. An MSI write cannot pass a DMA write, so the race is eliminated.

PCI defines two optional extensions to support Message Signalled Interrupts, MSI and MSI X. PCI Express defines its own message based mechanism to emulate legacy PCI interrupts.

MSI (first defined in PCI 2.2) permits a device to allocate 1, 2, 4, 8, 16 or 32 interrupts. The device is programmed with an address to write to (this address is generally a control register in an interrupt controller), and a 16 bit data word to identify it. The interrupt number is added to the data word to identify the interrupt.

MSI X (first defined in PCI 3.0) permits a device to allocate up to 2048 interrupts. The single address used by original MSI was found to be restrictive for some architectures. In particular, it made it difficult to target individual interrupts to different processors, which is helpful in some high speed networking applications. MSI X allows a larger number of interrupts and gives each one a separate target address and data word. Devices with MSI X do not necessarily support 2048 interrupts. Optional features in MSI (64 bit addressing and interrupt masking) are also mandatory with MSI X.

PCI Express does not have physical interrupt pins, but emulates the 4 physical interrupt pins of PCI via dedicated PCI Express Messages such as Assert INTA and Deassert INTC. Being message based (at the PCI Express layer), this mechanism provides some, but not all, of the advantages of the PCI layer MSI mechanism: the 4 virtual pins per device are no longer shared on the bus (although PCI Express controllers may still combine legacy interrupts internally), and interrupt changes no longer inherently suffer from race conditions. PCI Express permits devices to use these legacy interrupt messages, retaining software compatibility with PCI drivers, but they are required to also support MSI or MSI X in the PCI layer.

On Intel systems, the LAPIC must be enabled for the PCI (and PCI Express) MSI/MSI X to work, even on uniprocessor (single core) systems. In these systems, MSIs are handled by writing the interrupt vector directly into the LAPIC of the processor/core that needs to service the interrupt. The Intel LAPICs of 2009 supported up to 224 MSI based interrupts.