iAPX 432: Intel-дің тоқтатылған микропроцессор архитектурасы

Discontinued Intel microprocessor architecture

The iAPX 432 (Intel Advanced Performance Architecture) is a discontinued computer architecture introduced in 1981. It was Intel's first 32 bit processor design. The main processor of the architecture, the general data processor, is implemented as a set of two separate integrated circuits, due to technical limitations at the time. Although some early 8086, 80186 and 80286 based systems and manuals also used the iAPX prefix for marketing reasons, the iAPX 432 and the 8086 processor lines are completely separate designs with completely different instruction sets. The project started in 1975 as the 8800 (after the 8008 and the 8080) and was intended to be Intel's major design for the 1980s. Unlike the 8086, which was designed the following year as a successor to the 8080, the iAPX 432 was a radical departure from Intel's previous designs meant for a different market niche, and completely unrelated to the 8080 or x86 product lines. The iAPX 432 project is considered a commercial failure for Intel, and was discontinued in 1986.

The iAPX 432 was referred to as a "micromainframe", designed to be programmed entirely in high level languages. The instruction set architecture was also entirely new and a significant departure from Intel's previous 8008 and 8080 processors as the iAPX 432 programming model is a stack machine with no visible general purpose registers. It supports object oriented programming, written entirely in Ada, and Ada was also the intended primary language for application programming. In some aspects, it may be seen as a high level language computer architecture. These properties and features resulted in a hardware and microcode design that was more complex than most processors of the era, especially microprocessors. However, internal and external buses are (mostly) not wider than 16 bit, and, just like in other 32 bit microprocessors of the era (such as the 68000 or the 32016), 32 bit arithmetical instructions are implemented by a 16 bit ALU, via random logic and microcode or other kinds of sequential logic. The iAPX 432 enlarged address space over the 8080 was also limited by the fact that linear addressing of data could still only use 16 bit offsets, somewhat akin to Intel's first 8086 based designs, including the contemporary 80286 (the new 32 bit segment offsets of the 80386 architecture was described publicly in detail in 1984). Using the semiconductor technology of its day, Intel's engineers weren't able to translate the design into a very efficient first implementation. Along with the lack of optimization in a premature Ada compiler, this contributed to rather slow but expensive computer systems, performing typical benchmarks at roughly 1/4 the speed of the new 80286 chip at the same clock frequency (in early 1982). Originally designed for clock frequencies of up to 10 MHz, actual devices sold were specified for maximum clock speeds of 4 MHz, 5 MHz, 7 MHz and 8 MHz with a peak performance of 2 million instructions per second at 8 MHz.

Intel's 432 project started in 1976, a year after the 8 bit Intel 8080 was completed and a year before their 16 bit 8086 project began. The 432 project was initially named the 8800,

The iAPX 432 development team was managed by Bill Lattin, with Justin Rattner as the lead engineer (although one source Pollack later specialized in superscalarity and became the lead architect of the i686 chip Intel Pentium Pro. According to the New York Times, "the i432 ran 5 to 10 times more slowly than its competitor, the Motorola 68000".

Software running on the 432 does not need to explicitly deallocate objects that are no longer needed. Instead, the microcode implements part of the marking portion of Edsger Dijkstra's on the fly parallel garbage collection algorithm (a mark and sweep style collector). The entries in the system object table contain the bits used to mark each object as being white, black, or grey as needed by the collector. The iMAX 432 operating system includes the software portion of the garbage collector.

Executable instructions are contained within a system "instruction object". Due to instructions being bit aligned, a 16 bit bit displacement into the instruction object allows the object to contain up to 65,536 bits (8,192 bytes) of instructions. Instructions consist of an operator, consisting of a class and an opcode, and zero to three operand references. "The fields are organized to present information to the processor in the sequence required for decoding". More frequently used operators are encoded using fewer bits. The instruction begins with the 4 or 6 bit class field which indicates the number of operands, called the order of the instruction, and the length of each operand. This is optionally followed by a 0 to 4 bit format field which describes the operands (if there are no operands the format is not present). Then come zero to three operands, as described by the format. The instruction is terminated by the 0 to 5 bit opcode, if any (some classes contain only one instruction and therefore have no opcode). "The Format field permits the GDP to appear to the programmer as a zero , one , two , or three address architecture." The format field indicates that an operand is a data reference, or the top or next to top element of the operand stack.