Verilog тілі: Электрондық жүйелерді сипаттау құралы

Hardware description language

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register transfer level of abstraction. It is also used in the verification of analog circuits and mixed signal circuits, as well as in the design of genetic circuits. In 2009, the Verilog standard (IEEE 1364 2005) was merged into the SystemVerilog standard, creating IEEE Standard 1800 2009. Since then, Verilog has been officially part of the SystemVerilog language. The current version is IEEE standard 1800 2023. Chi Lai Huang had earlier worked on a hardware description LALSD, a language developed by Professor S. Y. H. Su, for his PhD work. The rights holder for this process, at the time proprietary, was "Automated Integrated Design Systems" (later renamed to Gateway Design Automation in 1985). Gateway Design Automation was purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog XL, the HDL simulator that would become the de facto standard (of Verilog logic simulators) for the next decade. Originally, Verilog was only intended to describe and allow simulation; the automated synthesis of subsets of the language to physically realizable structures (gates etc.) was developed after the language had achieved widespread usage. Verilog is a portmanteau of the words "verification" and "logic".

With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364 1995, commonly referred to as Verilog 95. In the same time frame Cadence initiated the creation of Verilog A to put standards support behind its analog simulator Spectre. Verilog A was never intended to be a standalone language and is a subset of Verilog AMS which encompassed Verilog 95.

Extensions to Verilog 95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became IEEE Standard 1364 2001 known as Verilog 2001. Verilog 2001 is a significant upgrade from Verilog 95. First, it adds explicit support for (2's complement) signed nets and variables. Previously, code authors had to perform signed operations using awkward bit level manipulations (for example, the carry out bit of a simple 8 bit addition required an explicit description of the Boolean algebra to determine its correct value). The same function under Verilog 2001 can be more succinctly described by one of the built in operators: +, , /, *, >>>. A generate–endgenerate construct (similar to VHDL's generate–endgenerate) allows Verilog 2001 to control instance and statement instantiation through normal decision operators (case–if–else). Using generate–endgenerate, Verilog 2001 can instantiate an array of instances, with control over the connectivity of the individual instances. File I/O has been improved by several new system tasks. And finally, a few syntax additions were introduced to improve code readability (e. g. always, @*, named parameter override, C style function/task/module header declaration). Verilog 2001 is the version of Verilog supported by the majority of commercial EDA software packages.

Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364 2005) consists of minor corrections, spec clarifications, and a few new language features (such as the uwire keyword). A separate part of the Verilog standard, Verilog AMS, attempts to integrate analog and mixed signal modeling with traditional Verilog.

The advent of hardware verification languages such as OpenVera, and Verisity's e language encouraged the development of Superlog by Co Design Automation Inc (acquired by Synopsys). The foundations of Superlog and Vera were donated to Accellera, which later became the IEEE standard P1800 2005: SystemVerilog. SystemVerilog is a superset of Verilog 2005, with many new features and capabilities to aid design verification and design modeling. As of 2009, the SystemVerilog and Verilog language standards were merged into SystemVerilog 2009 (IEEE Standard 1800 2009).

The SystemVerilog standard was subsequently updated in 2012, 2017, and most recently in December 2023.

The IEEE 1364 standard defines a four valued logic with four states: 0, 1, Z (high impedance), and X (unknown logic value). For the competing VHDL, a dedicated standard for multi valued logic exists as IEEE 1164 with nine levels.

The PLI provides a programmer with a mechanism to transfer control from Verilog to a program function written in C language. It is officially deprecated by IEEE Std 1364 2005 in favor of the newer Verilog Procedural Interface, which completely replaces the PLI. The PLI (now VPI) enables Verilog to cooperate with other programs written in the C language such as test harnesses, instruction set simulators of a microcontroller, debuggers, and so on. For example, it provides the C functions tf putlongp and tf getlongp which are used to write and read the 64 bit integer argument of the current Verilog task or function, respectively. For 32 bit integers, tf putp and tf getp are used.

For information on Verilog simulators, see the list of Verilog simulators.

– The official standard for Verilog 2005 (not free). IEEE P1364 – Working group for Verilog (inactive). IEEE P1800 – Working group for SystemVerilog (replaces above). Verilog syntax – A 1995 description of the syntax in Backus Naur form. This predates the IEEE 1364 standard.

Verilog AUTOs — An open source meta comment used by industry IP to simplify maintaining Verilog code.