IBM POWER6 процессоры: Техникалық сипаттамалары мен ерекшеліктері

2007 family of multiprocessors by IBM

The POWER6 is a microprocessor developed by IBM that implemented the Power ISA v.2.05. When it became available in systems in 2007, it succeeded the POWER5+ as IBM's flagship Power microprocessor. It is claimed to be part of the eCLipz project, said to have a goal of converging IBM's server hardware where practical (hence "ipz" in the acronym: iSeries, pSeries, and zSeries).

POWER6 was described at the International Solid State Circuits Conference (ISSCC) in February 2006, and additional details were added at the Microprocessor Forum in October 2006 and at the next ISSCC in February 2007. It was formally announced on May 21, 2007. It was released on June 8, 2007 at speeds of 3.5, 4.2 and 4.7 GHz, but the company has noted prototypes have reached 6 GHz. POWER6 reached first silicon in the middle of 2005, and was bumped to 5.0 GHz in May 2008 with the introduction of the P595.

The POWER6 is a dual core processor. Each core is capable of two way simultaneous multithreading (SMT). The POWER6 has approximately 790 million transistors and is 341 mm2 large fabricated on a 65 nm process. A notable difference from POWER5 is that the POWER6 executes instructions in order instead of out of order. This change often requires software to be recompiled for optimal performance, but the POWER6 still achieves significant performance improvements over the POWER5+ even with unmodified software, according to the lead engineer on the POWER6 project. Each core has a 64 KB, four way set associative instruction cache and a 64 KB data cache of an eight way set associative design with a two stage pipeline supporting two independent 32 bit reads or one 64 bit write per cycle. Each core has semi private 4 MiB unified L2 cache, where the cache is assigned a specific core, but the other has a fast access to it. The two cores share a 32 MiB L3 cache which is off die, using an 80 GB/s bus. POWER6 can connect to up to 31 other processors using two inter node links (50 GB/s), and supports up to 10 logical partitions per core (up to a limit of 254 per system). There is an interface to a service processor that monitors and adjusts performance and power according to set parameters. IBM also makes use of a 5 GHz duty cycle correction clock distribution network for the processor. In the network, the company implements a copper distribution wire that is 3 μm wide and 1.2 μm thick. The POWER6 design uses dual power supplies, a logic supply in the 0.8 to 1.2 Volt range and an SRAM power supply at about 150 mV higher.

The slightly enhanced POWER6+ was introduced in April 2009, but had been shipping in Power 560 and 570 systems since October 2008. It added more memory keys for secure memory partition, a feature taken from IBM's mainframe processors.

as of 2008, the range of POWER6 systems includes "Express" models (the 520, 550 and 560) and Enterprise models (the 570 and 595). The various system models are designed to serve any sized business. For example, the 520 Express is marketed to small businesses while the Power 595 is marketed for large, multi environment data centers. The main difference between the Express and Enterprise models is that the latter include Capacity Upgrade on Demand (CUoD) capabilities and hot pluggable processor and memory "books". +IBM POWER6 (Power Systems) servers Name Number of sockets Number of cores CPU clock frequency 520 Express 2 4 4.2 GHz or 4.7 GHz 550 Express 4 8 4.2 GHz or 5.0 GHz 560 Express 8 16 3.6 GHz 570 8 16 4.4 GHz or 5.0 GHz 570 16 32 4.2 GHz 575 16 32 4.7 GHz 595 32 64 4.2 GHz or 5.0 GHz

IBM also offers four POWER6 based blade servers. Specifications are shown in the table below. +IBM POWER6 blade servers Name Number of cores CPU clock frequency Blade slots required BladeCenter JS12 2 3.8 GHz 1 BladeCenter JS22 4 4.0 GHz 1 BladeCenter JS23 4 4.2 GHz 1 BladeCenter JS43 8 4.2 GHz 2

All blades support AIX, IBM i, and Linux. The BladeCenter S and H chassis is supported for blades running AIX, i, and Linux. The BladeCenter E, HT, and T chassis support blades running AIX and Linux but not i. At the SuperComputing 2007 (SC07) conference in Reno a new water cooled Power 575 was revealed. The 575 is composed of 2U "nodes" each with 32 POWER6 cores at 4.7 GHz with up to 256 GB of RAM. Up to 448 cores can be installed in a single frame. +IBM POWER6 disk storage Name Number of cores CPU clock frequency Number of controllers DS8700 2, 4 4.7 GHz 1, 2 DS8800 2, 4, 8 5.0 GHz 1, 2