Minimig

Open source re implementation of an Amiga 500

Minimig (short for Mini Amiga) is an open source re implementation of an Amiga 500 using a field programmable gate array (FPGA). Minimig started around January 2005 as a proof of concept by Dutch electrical engineer Dennis van Weeren. He intended Minimig as the answer to the ongoing discussions within the Amiga community on implementing the Amiga custom chipset using an FPGA. The project's source code and schematics were released under version 3 of the GNU General Public Licence on 25 July 2007.

As of Minimig rev1.0 board:
Xilinx Spartan 3 400k gate (XC3S400 4PQ208C) FPGA using 82% capacity. Freescale MC68SEC000, 3.3V, at 7.09379 MHz. However, there's no 'E' clock, MOVE sr,<EA> is privileged and there is no real replacement instruction. This does not seem to affect any programs yet. Amiga Chip RAM bus and Slow RAM merged into a single synchronous bus running at 7.09379 MHz. 2 MB 70 ns asynchronous SRAM organised as 2x 524 288 x 16 bit banks. MCU PIC 18LF252 I/SP (An alternative is Atmel AVR) implements a FAT16 disk layout and handles loading of FPGA configuration and Kickstart. Simulates a floppy to the Amiga by encoding on the fly from ADF files. MMC Flash memory card to load FPGA configuration, kickstart and software for the implemented computer. 3× LEDs to display the disk activity, main power and Amiga power up status (no existing audio filter!) Amiga power up status led will change intensity to show audio filter status. Video D/A consists of 4 resistors for each color red, green, blue (4 bits/color) and output via VGA connector. Audio from an 8 bit dithering sigma delta converter with 2nd order analogue filter. +5V DC main power (~200 mA).

Motorola 68000 type CPU. Hardware OCS and ECS, PAL & NTSC video switchable via OSD. 512 KB SRAM for Kickstart used as ROM. 0 1536 KB Slow RAM expansion (originally 512 KB). 512 2048 KB Chip RAM (originally 1024 KB). On screen display offers selection of ADF disk images from the SD/MMC card using the keyboard or a joystick.

Date Event2005 03 06Verilog sources coding started.2005 12 05Announcement of the project.2006 SpringVerilog sources completed. 2006 06 11Screenshoot of schematic for board v1.0 published.2006 10 15Schematic for board v1.0 completed.2007 06 xxSources predicted to be released, but weren't.2007 07 04Last source edit (core).2007 07 13Busy making website for the project.2007 07 24Minimig sources released on the official website.

Several issues remain. It needs a binary copy of the AmigaOS kickstart ROM from a real Amiga 500 or free re implementation like AROS 68k which is not yet fully compatible but which continually improves. The current firmware for loading ROM and floppy images is limited to a single root directory and 8.3 filenames.

Possible developments include a faster CPU, ECS chipset, AGA graphics (new FPGA board is required), hard disk, ethernet, small RISC Core for enhanced AROS functions etc. Use of a free kickstart replacement (e. g. AROS). A networked version would eliminate the need for swapping flash memories.

On 3 September 2008, a new FPGA core enables read/write support, as well as some chipset improvements.

On 22 December 2008, a replacement board that fits in the PIC (MCU) controller socket were announced. It makes hard drive, 4x floppy disk and write support possible. The FPGA core is the same for the new ARM and PIC firmware but only the ARM has enough resources to support four drives. The PIC only supports two. The upgrade also allows one to select to increase the CPU speed from 7.09 to 49.63 MHz with a 4 KB zero waitstate CPU cache. But it requires an FPGA core to actually carry it out (which works with the 16 MHz 68SEC000 chips). The hard drive support is available by a virtual A600/A1200 style GAYLE parallel ATA interface. Up to 551 KB/s

The Minimig port for the MiST board supports USB peripherals including USB mice, USB keyboards and USB mice as well as a physical MIDI interface.

On 22 December 2008, a modification of the original PCB by piggybacking another set of SRAM chips enables up to 4 MiB of RAM in total. An unreleased Minimig core has been upgraded with AGA support and extended to support at least 50 MiB of Chip memory on the prototype Replay board designed by Mike Johnson at FPGA Arcade.

Jeri Ellsworth, who designed the C64 Direct to TV Commodore 64 on a chip ASIC, had a working Amiga on a chip prototype in 2003. Except for the 68000 processor and disk interface, everything was emulated inside a FPGA. However, the project was never finished or turned into an ASIC. Illuwatar, a small private hardware designer in Sweden, implemented a Mini ITX form factor version of the Minimig under the Open Source design License. This hardware version fits in standard Mini ITX cases and has dimensions of 17 cm x 17 cm. Connecting ports in this version were moved to the back of the mainboard to comply with Mini ITX requirements. On 9 Feb 2008 ACube Systems announced the availability of finished Minimig v1.1 boards. On 2006 10 11 Jens Schönfeld at Individual Computers revealed that they had been working on a commercial Amiga in FPGA for the past year called "Clone A" that is similar to Minimig. In contrast to Minimig, Individual Computers's Clone A was developed by a three person development team employing a powerful logic analyzer. The system will use clone chips to replace CIAs, Paula, Gary, Agnus and Denise. The CPU will be the original from Motorola. Final chips will also include AGA and a working parallel port to enable 4 player games. Still unreleased since 2015. Wolfgang Förster has completed the Suska project, which is an Atari ST on FPGA. Inspired by Minimig Till Harbaum invented MIST, an open FPGA based implementation of Atari ST and Amiga intended to have a low price and be easy built at home. Different than Minimig, the 68000 CPU is not present as physical device but implemented inside the FPGA. Inspired by MIST Alexey Melnikov invented MiSTer, an FPGA based implementation of Atari ST and Amiga, based on a commercial board by Terasic : DE10 nano. There are at least five so called "daughter boards" that enhance the capabilities of MiSTer. Vampire V4 Standalone, released by Apollo Team in 2019, provides ECS/AGA chipset re implementation, plus 68080 CPU and SAGA core, also using a field programmable gate array (FPGA).