Input–output memory management unit

Configuration in computing

In computing, an input–output memory management unit (IOMMU) is a memory management unit (MMU) connecting a direct memory access–capable (DMA capable) I/O bus to the main memory. Like a traditional MMU, which translates CPU visible virtual addresses to physical addresses, the IOMMU maps device visible virtual addresses (also called device addresses or memory mapped I/O addresses in this context) to physical addresses. Some units also provide memory protection from faulty or malicious devices. An example IOMMU is the graphics address remapping table (GART) used by AGP and PCI Express graphics cards on Intel Architecture and AMD computers. On the x86 architecture, prior to splitting the functionality of northbridge and southbridge between the CPU and Platform Controller Hub (PCH), I/O virtualization was not performed by the CPU but instead by the chipset.

When an operating system is running inside a virtual machine, including systems that use paravirtualization, such as Xen and KVM, it does not usually know the host physical addresses of memory that it accesses. This makes providing direct access to the computer hardware difficult, because if the guest OS tried to instruct the hardware to perform a direct memory access (DMA) using guest physical addresses, it would likely corrupt the memory, as the hardware does not know about the mapping between the guest physical and host physical addresses for the given virtual machine. The corruption can be avoided if the hypervisor or host OS intervenes in the I/O operation to apply the translations. However, this approach incurs a delay in the I/O operation. An IOMMU solves this problem by re mapping the addresses accessed by the hardware according to the same (or a compatible) translation table that is used to map guest physical address to host physical addresses.

AMD has published a specification for IOMMU technology, called AMD Vi. IBM offered Extended Control Program Support: Virtual Storage Extended (ECPS:VSE) mode on its 43xx line; channel programs used virtual addresses. Intel has published a specification for IOMMU technology as Virtualization Technology for Directed I/O, abbreviated VT d.
Information about the Sun IOMMU has been published in the Device Virtual Memory Access (DVMA) section of the Solaris Developer Connection. The IBM Translation Control Entry (TCE) has been described in a document entitled Logical Partition Security in the IBM eServer pSeries 690. The PCI SIG has relevant work under the terms Single Root I/O Virtualization (SR IOV) and Address Translation Services (ATS). These were formerly covered in distinct specifications, but as of PCI Express 5.0 have been moved to the PCI Express Base Specification. ARM defines its version of IOMMU as System Memory Management Unit (SMMU) to complement its Virtualization architecture.