Successive-approximation ADC

Type of analog to digital converter

A successive approximation ADC is a type of analog to digital converter (ADC) that converts a continuous analog waveform into a discrete digital representation using a binary search through all possible quantization levels before finally converging upon a digital output for each conversion.

Example 1: The ten steps to converting an analog input to 10 bit digital, using successive approximation, are shown here for all voltages from 5 V to 0 V in 0.1 V iterations. Since the reference voltage is 5 V, when the input voltage is also 5 V, all bits are set. As the voltage is decreased to 4.9 V, only some of the least significant bits are cleared. The MSB will remain set until the input is one half the reference voltage, 2.5 V.

The binary weights assigned to each bit, starting with the MSB, are 2.5, 1.25, 0.625, 0.3125, 0.15625, 0.078125, 0.0390625, 0.01953125, 0.009765625, 0.0048828125. All of these add up to 4.9951171875, meaning binary 1111111111, or one LSB less than 5. When the analog input is being compared to the internal DAC output, it effectively is being compared to each of these binary weights, starting with the 2.5 V and either keeping it or clearing it as a result. Then by adding the next weight to the previous result, comparing again, and repeating until all the bits and their weights have been compared to the input, the result, a binary number representing the analog input, is found. Example 2: The working of a 4 bit successive approximation ADC is illustrated below. The MSB is initially set to 1 whereas the remaining digits are set to zero. If the input voltage is lower than the value stored in the register, on the next clock cycle, the register changes its value to that illustrated in the figure by following the green line. If the input voltage is higher, then on the next clock cycle, the register changes its value to that illustrated in the figure by following the red line. The simplified structure of this type of ADC that acts on 1=2^(n) volts range can be expressed as an algorithm:

Initialize register with MSB set to 1 and all other values set to zero. In n th clock cycle, if voltage is higher than digital equivalent voltage of the number in register, the (n+1) th digit from the left is set to 1. If the voltage were lower than digital equivalent voltage, then n th digit from left is set to zero and the next digit is set to 1. To perform a conversion, an N bit ADC requires N such clock cycles excluding the initial state. The successive approximation ADC can be alternatively explained by first uniformly assigning each digital output to corresponding ranges as shown. It can be seen that the algorithm essentially divides the voltage range into two regions and checks which of the two regions the input voltage belongs to. Successive steps involve taking the identified region from before and further dividing the region into two and continuing identification. This occurs until all possible choices of digital representations are exhausted, leaving behind an identified region that corresponds to only one of the digital representations.

Counter type ADC: The D to A converter can be easily turned around to provide the inverse function A to D conversion. The principle is to adjust the DAC's input code until the DAC's output comes within LSB to the analog input which is to be converted to binary digital form. Servo tracking ADC: It is an improved version of a counting ADC. The circuit consists of an up down counter with the comparator controlling the direction of the count. The analog output of the DAC is compared with the analog input. If the input is greater than the DAC output signal, the output of the comparator goes high and the counter is caused to count up. The tracking ADC has the advantage of being simple. The disadvantage, however, is the time needed to stabilize as a new conversion value is directly proportional to the rate at which the analog signal changes.

One of the most common implementations of the successive approximation ADC, the charge redistribution successive approximation ADC, uses a charge scaling DAC. The charge scaling DAC simply consists of an array of individually switched binary weighted capacitors. The amount of charge upon each capacitor in the array is used to perform the aforementioned binary search in conjunction with a comparator internal to the DAC and the successive approximation register. The capacitor array is completely discharged to the offset voltage of the comparator, VOS. This step provides automatic offset cancellation (i. e. the offset voltage represents nothing but dead charge, which can't be juggled by the capacitors). All of the capacitors within the array are switched to the input signal Vin. The capacitors now have a charge equal to their respective capacitance times the input voltage minus the offset voltage upon each of them. The capacitors are then switched so that this charge is applied across the comparator input, creating a comparator input voltage equal to −Vin. The actual conversion process proceeds. First, the MSB capacitor is switched to Vref, which corresponds to the full scale range of the ADC. Due to the binary weighting of the array, the MSB capacitor forms a 1:1 charge divider with the rest of the array. Thus, the input voltage to the comparator is now Subsequently, if Vin is greater than Vref/2, then the comparator outputs a digital 1 as the MSB, otherwise it outputs a digital 0 as the MSB. Each capacitor is tested in the same manner until the comparator input voltage converges to the offset voltage, or at least as close as possible given the resolution of the DAC.

When implemented as an analog circuit – where the value of each successive bit is not perfectly 2^(N) (e. g. 1.1, 2.12, 4.05, 8.01, etc.) – a successive approximation approach might not output the ideal value because the binary search algorithm incorrectly removes what it believes to be half of the values the unknown input cannot be. Depending on the difference between actual and ideal performance, the maximal error can easily exceed several LSBs, especially as the error between the actual and ideal 2^(N) becomes large for one or more bits. Since the actual input is unknown, it is therefore very important that accuracy of the analog circuit used to implement a SAR ADC be very close to the ideal 2^(N) values; otherwise, it cannot guarantee a best match search.