PowerPC G4: История и применение микропроцессора

Microprocessor

PowerPC G4 is a designation formerly used by Apple to describe a fourth generation of 32 bit PowerPC microprocessors. Apple has applied this name to various (though closely related) processor models from Freescale, a former part of Motorola. Motorola and Freescale's proper name of this family of processors is PowerPC 74xx. Macintosh computers such as the PowerBook G4 and iBook G4 laptops and the Power Mac G4 and Power Mac G4 Cube desktops all took their name from the processor. PowerPC G4 processors were also used in the eMac, first generation Xserves, first generation Mac Minis, and the iMac G4 before the introduction of the PowerPC 970. Apple completely phased out the G4 series for desktop models after it selected the 64 bit IBM produced PowerPC 970 processor as the basis for its PowerPC G5 series. The last desktop model that used the G4 was the Mac Mini. The last portable to use the G4 was the iBook G4, which was replaced by the Intel based MacBook. The PowerBook G4 was replaced by the Intel based MacBook Pro. The PowerPC G4 processors are also popular in other computer systems, such as the AmigaOne series of computers and the Pegasos from Genesi. Besides desktop computers the PowerPC G4 is popular in embedded environments, like routers, telecom switches, imaging, media processing, avionics and military applications, where one can take advantage of the AltiVec and its SMP capabilities.

The PowerPC 7400 (code named "Max") debuted in August 1999 and was the first processor to carry the "G4" moniker. The chip operates at speeds ranging from 350 to 500 MHz and contains 10.5 million transistors, manufactured using Motorola's 0.20 μm HiPerMOS6 process. The die measures 83 mm2 and features copper interconnects. Motorola had promised Apple to deliver parts with speed up to 500 MHz, but yields proved too low initially. This forced Apple to take back the advertised 500 MHz models of Power Mac G4. The Power Mac series was downgraded abruptly from 400, 450, and 500 MHz processor speeds to 350, 400, and 450 MHz while problems with the chip were ironed out. The incident generated a rift in the Apple Motorola relationship, and reportedly caused Apple to ask IBM for assistance to get the production yields up on the Motorola 7400 series line. The 500 MHz model was reintroduced on February 16, 2000.

Much of the 7400 design was done by Motorola in close co operation with Apple and IBM. IBM, the third member of the AIM alliance, designed the chip together with Motorola in its Somerset design center, but chose not to manufacture it, because it did not see the need back then for the Vector Processing Unit. Ultimately, the G4 architecture design contained a 128 bit vector processing unit labelled AltiVec by Motorola while Apple marketing referred to it as the "Velocity Engine". The PowerPC 970 (G5) was the first IBM manufactured CPU to implement VMX/AltiVec, for which IBM reused the old 7400 design they still had from the design they did with Motorola in Somerset. The Xenon CPU in the Xbox 360 also features VMX, with added proprietary extensions made especially for Microsoft. POWER6, introduced in 2007, is IBM's first "big iron" CPU to also implement VMX. With the AltiVec unit, the 7400 microprocessor can do four way single precision (32 bit) floating point math, or 16 way 8 bit, 8 way 16 bit or four way 32 bit integer math in a single cycle. Furthermore, the vector processing unit is superscalar, and can do two vector operations at the same time. Compared to Intel's x86 microprocessors at the time, this feature offered a substantial performance boost to applications designed to take advantage of the AltiVec unit. Some examples are Adobe Photoshop which utilises the AltiVec unit for faster rendering of effects and transitions, and Apple's iLife suite which takes advantage of the unit for importing and converting files on the fly. Additionally, the 7400 has enhanced support for symmetric multiprocessing (SMP) thanks to an improved cache coherency protocol (MERSI) and a 64 bit floating point unit (FPU), derived in part from the 604 series. The 603 series had a 32 bit FPU, which took two clock cycles to accomplish 64 bit floating point arithmetic. The PowerPC G4 family supports two bus technologies, the older 60x bus which it shares with the PowerPC 600 and PowerPC 7xx families, and the more advanced MPX bus. Devices that utilize the 60x bus can be made compatible with either 6xx or 7xx processors, enabling a wide variety of offerings and a clear and cheap upgrade path while keeping compatibility issues at a minimum. There are primarily two companies manufacturing system controllers for 7xx and 7xxx computers, Tundra with their Tsi1xx controllers and Marvell with their Discovery controllers.

The PowerPC 7410 "Nitro" is a low power version of the 7400 but it was manufactured at 180 nm instead of 200 nm. Like the 7400 it has 10.5 million transistors. It debuted in the PowerBook G4 on 9 January 2001. The chip added the ability to use all or half of its cache as high speed, non cached memory mapped to the processor's physical address space as desired. This feature was used by embedded systems vendors such as Mercury Computer Systems.

The PowerPC 7450 "Voyager"/"V'ger" was the only major redesign of the G4 processor. The 33 million transistor chip extended significantly the execution pipeline of 7400 (7 vs. 4 stages minimum) to reach higher clock speeds, improved instruction throughput (3 + branch vs. 2 + branch per cycle) to compensate for higher instruction latency, replaced an external L2 cache (up to 2 MB 2 way set associative, 64 bit data path) with an integrated one (256 KB 8 way set associative, 256 bit data path), supported an external L3 cache (up to 2 MB 8 way set associative, 64 bit data path), and featured many other architectural advancements. The AltiVec unit was improved with the 7450; instead of executing one vector permute instruction and one vector ALU (simple int, complex int, float) instruction per cycle like 7400/7410, the 7450 and its Motorola/Freescale followers can execute two arbitrary vector instructions simultaneously (permute, simple int, complex int, float). It was introduced with the 733 MHz Power Mac G4 on 9 January 2001. Motorola followed with an interim release, the 7451, codenamed "Apollo 6", just like the 7455. Early AmigaOne XE computers were shipped with the 7451 processor. The enhancements to the 745x design gave it the nicknames G4e or G4+ but these were never official designations.

The PowerPC 7447 "Apollo 7" is slightly improved from the 7450/55, it has a 512 KB on chip L2 cache and was manufactured in a 130 nm process with SOI, hence drawing less power. It has 58 million transistors. With the 7447A, which introduced an integrated thermal diode as well as DFS (dynamic frequency scaling) Freescale was able to reach a slightly higher clock. The 7447B is effectively a 7447A with even higher frequency scaling, with clock rates up to 1.7 GHz officially and easily up to 2.4 GHz through overclocking. The 7457 and 7457A have an additional L3 cache interface, supporting up to 4 MB of L3 cache, up from 2 MB supported by the 7455 and 7450. However, its frequency scaling stagnated when Apple chose to use the 7447(s) instead of the 7457(s), despite the 7457 being the L3 cache enabled successor to the L3 cache enabled 7455 that Apple used before. The only companies that offer the 7457 in the form of upgrades for the Power Mac G4, iMac G4, and Power Mac G4 Cube are Giga Designs, Sonnet Technology, Daystar Technology (they use the 7457 only for iMac G4 upgrades) and PowerLogix. The Pegasos computer platform from Genesi also uses 7447 in its Pegasos II/G4. The 7457 is often used to repair an AmigaOne XE CPU module; some AmigaOS software with the 7457 installed may mistake the AmigaOne for a Pegasos II computer as there were never any official 7457 boards released by Eyetech.

In 2004, Freescale renamed the G4 core to e600 and changed its focus from general CPUs to high end embedded SoC devices, and introduced a new naming scheme, MPC86xx. The 7448 was to be the last pure G4 and it formed the base of the new e600 core with a seven stage, three issue pipeline, and a powerful branch prediction unit which handles up to sixteen instructions out of order. It has an enhanced AltiVec unit capable of limited out of order execution and a 1 MB L2 cache.