Coreboot: Открытая прошивка для компьютеров

Open source computer firmware

coreboot, formerly known as LinuxBIOS, is a software project aimed at replacing proprietary firmware (BIOS or UEFI) found in most computers with a lightweight firmware designed to perform only the minimum number of tasks necessary to load and run a modern 32 bit or 64 bit operating system. Since coreboot initializes the bare hardware, it must be ported to every chipset and motherboard that it supports. As a result, coreboot is available only for a limited number of hardware platforms and motherboard models. One of the coreboot variants is Libreboot, a software distribution partly free of proprietary blobs, aimed at end users.

The coreboot project began with the goal of creating a BIOS that would start fast and handle errors intelligently. It is licensed under the terms of the GNU General Public License version 2 (GPLv2). Main contributors include LANL, SiS, AMD, Coresystems and Linux Networx, Inc, as well as motherboard vendors MSI, Gigabyte and Tyan, which offer coreboot alongside their standard BIOS or provide specifications of the hardware interfaces for some of their motherboards. Google partly sponsors the coreboot project. CME Group, a cluster of futures exchanges, began supporting the coreboot project in 2009. Other than the first three models, all Chromebooks run coreboot. Code from Das U Boot has been assimilated to enable support for processors based on the ARM instruction set. In June 2019, coreboot began to use the NSA software Ghidra for its reverse engineering efforts on firmware specific problems following the release of the suite as free and open source software.

coreboot typically loads a Linux kernel, but it can load any other stand alone ELF executable, such as iPXE, gPXE or Etherboot that can boot a Linux kernel over a network, or SeaBIOS that can load a Linux kernel, Windows 2000 and later, and BSDs; Windows 2000/XP and OpenBSD support was previously provided by ADLO. coreboot can also load a kernel from any supported device, such as Myrinet, Quadrics, or SCI cluster interconnects. Booting other kernels directly is also possible, such as a Plan 9 kernel. Instead of loading a kernel directly, coreboot can pass control to a dedicated boot loader, such as a coreboot capable version of GNU GRUB 2.

coreboot is written primarily in C, with a small amount of assembly code. Choosing C as the primary programming language enables easier code audits when compared to contemporary PC BIOS that was generally written in assembly, which results in improved security. There is build and runtime support to write parts of coreboot in Ada to further raise the security bar, but it is currently only sporadically used. The source code is released under the GNU GPL version 2 license. coreboot performs the absolute minimal amount of hardware initialization and then passes control to the operating system. As a result, there is no coreboot code running once the operating system has taken control. A feature of coreboot is that the x86 version runs in 32 bit mode after executing only ten instructions (almost all other x86 BIOSes run exclusively in 16 bit mode). This is similar to the modern UEFI firmware, which is used on newer PC hardware.

The most difficult hardware that coreboot initializes is the DRAM controllers and DRAM. In some cases, technical documentation on this subject is NDA restricted or unavailable. RAM initialization is particularly difficult because before the RAM is initialized it cannot be used. Therefore, to initialize DRAM controllers and DRAM, the initialization code may have only the CPU's general purpose registers or Cache as RAM as temporary storage. romcc, a C compiler that uses registers instead of RAM, eases the task. Using romcc, it is relatively easy to make SMBus accesses to the SPD ROMs of the DRAM DIMMs, that allows the RAM to be used. With newer x86 processors, the processor cache can be used as RAM until DRAM is initialized. The processor cache has to be initialized into Cache as RAM mode as well, but this needs fewer instructions than initializing DRAM. Also, the Cache as RAM mode initialization is specific to CPU architectures, thus more generic than DRAM initialization, which is specific to each chipset and mainboard. For most modern x86 platforms, closed source binary only components provided by the vendor are used for DRAM setup. For Intel systems, FSP M is required, while AMD has no current support. Binary AGESA is currently used for proprietary UEFI firmware on AMD systems, and this model is expected to carry over to any future AMD related coreboot support.

There are also CPU emulators that either replace the CPU or connect via a JTAG port, with the Sage SmartProbe being an example. Code can be built on, or downloaded to, BIOS emulators rather than flashing the BIOS device.

One physical meeting is the European Coreboot Conference which was organized in October 2017 and lasted for three days.

Event and year Date Host city Venue Resources Themes ECC2017 26.10. – 29.10 Bochum, Germany RUB Convention Center https://ecc2017. com