Микропроцессор W65C02: Улучшенная CMOS версия 6502

CMOS microprocessor in the 6502 family

The Western Design Center (WDC) 65C02 microprocessor is an enhanced CMOS version of the popular nMOS based 8 bit MOS Technology 6502. It uses less power than the original 6502, fixes several problems, and adds new instructions. The power usage is on the order of 10 to 20 times less than the original 6502 running at the same speed; its reduced power consumption has made it useful in portable computer roles and industrial microcontroller systems. The 65C02 has also been used in some home computers, as well as in embedded applications, including medical grade implanted devices. Development of the WDC 65C02 began in 1981 with samples released in early 1983. The 65C02
was officially released sometime shortly after. WDC licensed the design to Synertek, NCR, GTE Microcircuits, and Rockwell Semiconductor. Rockwell's primary interest was in the embedded market and asked for several new commands to be added to aid in this role. These were later copied back into the baseline version, at which point WDC added two new commands of their own to create the W65C02. Sanyo later licensed the design as well, and Seiko Epson produced a further modified version as the HuC6280. Early versions used 40 pin DIP packaging, and were available in 1, 2 and 4 MHz versions, matching the speeds of the original nMOS versions. Later versions were produced in PLCC and QFP packages, as well as PDIP, and with much higher clock speed ratings. The current version from WDC, the W65C02S 14 has a fully static core and officially runs at speeds up to 14 MHz when powered at 5 volts.

The W65C02S may be operated at any convenient supply voltage (VDD) between 1.8 and 5 volts (±5%). The data sheet AC characteristics table lists operational characteristics at 5 V at 14 MHz, 3.3 V or 3 V at 8 MHz, 2.5 V at 4 MHz, and 1.8 V at 2 MHz. This information may be an artifact of an earlier data sheet, as a graph indicates that typical devices are capable of operation at higher speeds than suggested by the AC characteristics table, and that reliable operation at 20 MHz should be readily attainable with VDD at 5 volts, assuming the supporting hardware will allow it. The W65C02S support for arbitrary clock rates allows it to use a clock that runs at a rate ideal for some other part of the system, such as 13.5 MHz (digital SDTV luma sampling rate), 14.31818 MHz (NTSC colour carrier frequency × 4), 14.75 MHz (PAL square pixels), 14.7456 (baud rate crystal), etc., as long as VDD is sufficient to support the frequency. Designer Bill Mensch has pointed out that FMAX is affected by off chip factors, such as the capacitive load on the microprocessor's pins. Minimizing load by using short signal tracks and fewest devices helps raise FMAX. The PLCC and QFP packages have less pin to pin capacitance than the PDIP package, and are more economical in the use of printed circuit board space. WDC has reported that FPGA realizations of the W65C02S have been successfully operated at 200 MHz.

Although the 65C02 can mostly be thought of as a low power 6502, it also fixes several bugs found in the original and adds new instructions, addressing modes and features that can assist the programmer in writing smaller and faster executing programs. It is estimated that the average 6502 assembly language program can be made 10 to 15 percent smaller on the 65C02 and see a similar improvement in performance, largely through avoided memory accesses through the use of fewer instructions to accomplish a given task.

The original 6502 has 56 instructions, which, when combined with different addressing modes, produce a total of 151 opcodes of the possible 256 8 bit opcode patterns. The remaining 105 unused opcodes are undefined, with the set of codes with low order 4 bits with 3, 7, B or F left entirely unused, the code with low order 2 having only a single opcode. On the 6502, some of these leftover codes actually perform computation. Due to the way the 6502's instruction decoder works, simply setting certain bits in the opcode cause parts of the instruction processing to take place. Some of these opcodes immediately crash the processor, while other perform useful functions and were even given unofficial assembler mnemonics by some programmers. The 65C02 adds new opcodes that use some of these previously undocumented instruction slots. For example, $FF is used for the new BBS instruction. Those which remain truly unused are equivalent to NOPs. 6502 programs using those opcodes will not work on the 65C02.

The original 6502 had several errata when initially launched. Early versions of the processor had no ROR (rotate right) instruction and MOS Technology manuals did not document it either. ROR was implemented very early in the production run and the vast majority of machines using the processor support this instruction. A bug that is present in all NMOS variants of the 6502 involves the jump instruction when using indirect addressing. In this addressing mode, the target address of the JMP instruction is fetched from memory, the jump vector, rather than being an operand to the JMP instruction. For example, JMP ($1234) would fetch the value in memory locations (least significant byte) and (most significant byte) and load those values into the program counter, which would then cause the processor to continue execution at the address stored in the vector. The bug appears when the vector address ends in , which is the boundary of a memory page. In this case, JMP will fetch the most significant byte of the target address from of the original page rather than of the new page. Hence JMP ($12FF) would get the least significant byte of the target address at and the most significant byte of the target address from rather than The 65C02 corrected this issue. More of an oversight than a bug, the state of the (D)ecimal flag in the NMOS 6502's status register is undefined after a reset or interrupt. This means programmers have to set the flag to a known value in order to avoid any bugs related to arithmetic operations. As a result, one finds a CLD instruction (CLear Decimal) in almost all 6502 interrupt handlers, as well as early in the reset code. The 65C02 automatically clears this flag after pushing the status register onto the stack in response any interrupt or in response to a hardware reset, thus placing the processor back into binary arithmetic mode. When executing a read modify write (R M W) instruction, such as INC addr, all NMOS variants will do a double write on addr, first rewriting the current value found at addr and then writing the modified value. This behavior can result in difficult to resolve bugs if addr is a hardware register. This may occur if the hardware is watching for changes to the value in the register and then performs an action, in this case, it will perform two actions, one with the original value and then again with the new value. The 65C02 instead performs a double read of addr, followed by a single write. When performing indexed addressing, if indexing crosses a page boundary all NMOS variants will read from an invalid address before accessing the correct address. As with a R M W instruction, this behavior can cause problems when accessing hardware registers via indexing. The 65C02 fixed this problem by performing a dummy read of the instruction opcode when indexing crosses a page boundary. However, this fix introduced a new bug that occurs when the base address is on an even page boundary (which means indexing will never cross into the next page). With the new bug, a dummy read is performed on the base address prior to indexing, such that LDA $1200,X will do a dummy read on prior to the value of X being added to Again, if indexing on hardware register addresses, this bug can result in undefined behavior. If an NMOS 6502 is fetching a BRK (software interrupt) opcode at the same time a hardware interrupt occurs, the BRK will be ignored as the processor reacts to the hardware interrupt. The 65C02 correctly handles this situation by servicing the interrupt and then executing BRK.

In addition to the new commands above, WDC also added the STP and WAI instructions for supporting low power modes. , STop the Processor, halted all processing until a hardware reset was issued. This could be used to put a system to "sleep" and then rapidly wake it with a reset. Normally this would require some external system to maintain main memory, and it was not widely used. t had a similar effect, entering low power mode, but this instruction woke the processor up again on the reception of an interrupt. Previously, handling an interrupt generally involved running a loop to check if an interrupt has been received, sometimes known as "spinning", checking the type when one is received, and then jumping to the processing code. This meant the processor was running during the entire process, even when no interrupts were occurring. In contrast, in the 65C02, interrupt code could be written by having a followed immediately by a or to the handler. When the was encountered, processing stopped and the processor went into low power mode. When the interrupt was received, it immediately processed the and handled the request. This had the added advantage of slightly improving performance. In the spinning case, the interrupt might arrive in the middle of one of the loop's instructions, and to allow it to restart after returning from the handler, the processor spends one cycle to save its location. With , the processor enters the low power state in a known location where all instructions are guaranteed to be complete, so when the interrupt arrives it cannot possibly interrupt an instruction and the processor can safely continue without spending a cycle saving state.

The 65SC02 is a variant of the WDC 65C02 without bit instructions.