Кража циклов процессора: методы доступа к памяти

hardware memory operations

In computing, traditionally cycle stealing is a method of accessing computer memory (RAM) or bus without interfering with the CPU. It is similar to direct memory access (DMA) for allowing I/O controllers to read or write RAM without CPU intervention. Clever exploitation of specific CPU or bus timings can permit the CPU to run at full speed without any delay if external devices access memory not actively participating in the CPU's current activity and complete the operations before any possible CPU conflict. Cycle stealing was common in older platforms, first on supercomputers which used complex systems to time their memory access, and later on early microcomputers where cycle stealing was used both for peripherals as well as display drivers. It is more difficult to implement in modern platforms because there are often several layers of memory running at different speeds, and access is often mediated by the memory management unit. In the cases where the functionality is needed, modern systems often use dual port RAM which allows access by two systems, but this tends to be expensive. In older references, the term is also used to describe traditional DMA systems where the CPU stops during memory transfers. In this case the device is stealing cycles from the CPU, so it is the opposite sense of the more modern usage. In the smaller models of the IBM System/360 and System/370, the control store contains microcode for both the processor architecture and the channel architecture. When a channel needs service, the hardware steals cycles from the CPU microcode in order to run the channel microcode.

Some processors were designed to allow cycle stealing, or at least supported it easily. This was the case for the Motorola 6800 and MOS 6502 systems due to a design feature which meant the CPU only accessed memory every other clock cycle. Using RAM that was running twice as fast as the CPU clock allowed a second system to interleave its accesses between the CPUs by timing themselves on every other clock cycle. This was widely used for updating the display using main memory as a framebuffer. Common RAM of the late 1970s ran at 2 MHz, so most machines had a CPU running around 1 MHz. The BBC Micro secured a supply of 4 MHz RAM which allowed its CPU to run at 2 MHz. Another common solution was to use separate banks of memory that stored instructions vs. data, or more than one pool of data. In these cases the I/O systems can access their data memory while the processor is using a different bank. One example is the Zilog Z80, whose M1 line indicates that the processor is reading instructions; if those instructions are in a different bank, or more commonly ROM, the I/O systems can access RAM without interfering with the processor.

Cycle stealing is difficult to achieve in modern systems due to many factors such as pipelining, where pre fetch and concurrent elements are constantly accessing memory, leaving few predictable idle times to sneak in memory access. DMA is the only formal and predictable method for external devices to access RAM. This term is less common in modern computer architecture (above 66 100 MHz), where the various external buses and controllers generally run at different rates, and CPU internal operations are no longer closely coupled to I/O bus operations.