Control register

Processor register which changes or controls the general behavior of a CPU

A control register is a processor register that changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.

The early CPU lacked dedicated control registers, and relied on a limited set of internal signals and flags. When IBM developed a paging versionIBM never shipped the 360/64 or 360/66, only the 360/67. of the System/360, they added 16 control registers to the design for what became the 360/67. IBM did not provide control registers on other S/360 models, but made them a standard part of System/370, although with different register and bit assignments. As IBM added new features to the architecture, e. g., DAS, S/370 XA, S/370 ESA, ESA/390, they added additional fields to the control registers. With z/Architecture, IBM doubled the control register size to 64 bits.

On the 360/67, CR0 and CR2 are used by address translation, CR 4 6 contain miscellaneous flags including interrupt masks and Extended Control Mode, and CR 8 14 contain the switch settings on the 2167 Configuration Unit.

Control Register 0 contains the address of the segment table for dynamic address translation.

Control register 2 is the Relocation exception address register.

CR4 is the extended mask register for channels 0 31. Each bit is the 1/0 channel mask for the corresponding channel.

CR5 is reserved for the extended mask register for channels 32–63. Each bit is the 1/0 channel mask for the corresponding channel.

CR6 contains two mode flags plus extensions to the PSW mask bits. + CR6 Flags and Masks Field Bit Description 0 0 Machine Check Mask Extension for Channel Controller o 1 1 Machine Check Mask Extension for Channel Controller 1 2 3 Reserved for channel controllers 2 3 4 7 Unassigned 8 8 Extended Control Mode 9 9 Configuration Control Bit 10 23 Unassigned 24 31 External interrupt masking 24 Timer 25 Interrupt Key 26 Malfunction Alert CPU 1 (Ext. Sig. 2) 27 Malfunction Alert CPU 2 (Ext. Sig. 3) 28 Reserved (Ext. Sig. 4) 29 Reserved (Ext. Sig. 5) 30 External Interrupt CPU 1, 2 (Ext. Sig. 6) 31 Reserved (Ext. Sig. 7)

The CR0 register is 32 bits long on the 386 and higher processors. On x64 processors in long mode, it (and the other control registers) is 64 bits long. CR0 has various control flags that modify the basic operation of the processor. Register CR0 is the 32 Bit version of the old Machine Status Word (MSW) register. The MSW register was expanded to the Control Register with the appearance of the i386 processor. Bit Name Full Name Description 0 PE Protected Mode Enable If 1, system is in protected mode, else, system is in real mode 1 MP Monitor co processor Controls interaction of WAIT/FWAIT instructions with TS flag in CR0 2 EM Emulation If set, no x87 floating point unit present, if clear, x87 FPU present 3 TS Task switched Allows saving x87 task context upon a task switch only after x87 instruction used 4 ET Extension type On the 386, it allowed to specify whether the external math coprocessor was an 80287 or 80387 5 NE Numeric error Enable internal x87 floating point error reporting when set, else enables PC style x87 error detection 16 WP Write protect When set, the CPU cannot write to read only pages when privilege level is 0 18 AM Alignment mask Alignment check enabled if AM set, AC flag (in EFLAGS register) set, and privilege level is 3 29 NW Not write through Globally enables/disable write through caching 30 CD Cache disable Globally enables/disable the memory cache 31 PG Paging If 1, enable paging and use the register, else disable paging.

Reserved, the CPU will throw a #UD exception when trying to access it.

Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs, the address the program attempted to access is stored in the CR2 register.

Used when virtual addressing is enabled, hence when the PG bit is set in CR0. CR3 enables the processor to translate linear addresses into physical addresses by locating the page directory and page tables for the current task. Typically, the upper 20 bits of CR3 become the page directory base register (PDBR), which stores the physical address of the first page directory. If the PCIDE bit in CR4 is set, the lowest 12 bits are used for the process context identifier (PCID).