AN/FSQ-32

the deployed vacuum tube centrals which preceded this planned system

The AN/FSQ 32 SAGE Solid State Computer (AN/FSQ 7A before December 1958, colloq. "Q 32") was a planned military computer of the United States Air Force. It was central for deployment to Super Combat Centers in nuclear bunkers and to some above ground military installations. In 1958, Air Defense Command planned to acquire 13 Q 32 centrals for several Air Divisions/Sectors.

By June 1963 the Time Sharing System (TSS) Model Zero was demonstrated after magnetic drums were added to the time sharing. Each user was given a priority based time slice, measured in milliseconds, when the user's program was written from the magnetic drums into much higher speed memory, processed, and then written back to the magnetic drums with any computational changes that had occurred. It was influenced by early experiments at Bolt, Beranek, and Newman, and the CTSS project at MIT. Terminals included several Teletype Model 33 ASRs.

After the SAGE Sector Warning Network for the 1st operational SAGE direction center used the 1st operational computer network (cf. the experimental networks for Bomarc test launches and SAGE compatibility tests), in October 1965 Lincoln Labs' used a TX 2 solid state computer tied to the Q 32 prototype for the first telecommunication of time packets.

The prototype was an IBM 4020 Military Computer that included a Central Processing Unit, memory, High Speed Input/Output, Low Speed Input/Output, and for both computer operations and maintenance, an Operations Console. The AN/FSQ 32 central would have included additional equipment such as display and console equipment for use by Air Defense Command, Army Air Defense Command, Federal Aviation Administration, and other personnel (e. g., at SCC/DCs, weapons direction consoles for dispatching/guiding manned interceptors, launching/guiding CIM 10 Bomarcs, and launching Nike surface to air missiles).

The Instruction set used a fixed length of one word providing 24 bits for the operation and 24 bits for the address. The address consisted of 18 bits (3 bytes) for the memory address, with other bits used for the specification of index registers and indirect addressing. The operation field provided the operation code and a variety of modifiers. Some modifiers allowed instructions to operate only on specific bytes of a word or on specific bits of a byte without separate masking operations. Other modifiers allowed the single 48 bit ALU to operate on a pair of 24 bit operands to facilitate vector operations. CPU controls included sense switches to control various software functions, a run/halt switch, and a switch, amplifier, and speaker assembly, to provide audio feedback or even play music, by connecting one of four bits in the main accumulator which could then be toggled under software control at an appropriate rate to produce whatever tones one wanted.

Memory was addressed by words, which were 48 bits long. Each word was divided into eight 6 bit bytes. A 6 bit byte, as opposed to the 8 bit byte in common use today, was common in IBM and other scientific computers of the time. The address space provided a maximum of 256K words. The prototype was equipped with 128k words (48 bits plus two parity bits) of memory that was oil and water cooled. Also considered as part of the memory subsystem in that they were addressed via fixed reserved memory addresses, were 4 48 position switch banks, in which a short program could be inserted, and a plug panel, similar to the one used in IBM Unit Record equipment, that had the capacity of 32 words, so longer bootstrap or diagnostic programs could be installed in plug panels which could then be inserted into the receptacle and used as a primitive ROM. The memory had a cycle time of 2.5 microseconds, and the lack of memory management was a limitation in the computer.