Қуатты MOSFET транзисторлары: даму тарихы мен қолданылуы

MOSFET that can handle significant power levels

A power MOSFET is a specific type of metal–oxide–semiconductor field effect transistor (MOSFET) designed to handle significant power levels. Compared to the other power semiconductor devices, such as an insulated gate bipolar transistor (IGBT) or a thyristor, its main advantages are high switching speed and good efficiency at low voltages. It shares with the IGBT an isolated gate that makes it easy to drive. They can be subject to low gain, sometimes to a degree that the gate voltage needs to be higher than the voltage under control. The design of power MOSFETs was made possible by the evolution of MOSFET and CMOS technology, used for manufacturing integrated circuits since the 1960s. The power MOSFET shares its operating principle with its low power counterpart, the lateral MOSFET. The power MOSFET, which is commonly used in power electronics, was adapted from the standard MOSFET and commercially introduced in the 1970s. The power MOSFET is the most common power semiconductor device in the world, due to its low gate drive power, fast switching speed, easy advanced paralleling capability, wide bandwidth, ruggedness, easy drive, simple biasing, ease of application, and ease of repair. In 1969, Hitachi introduced the first vertical power MOSFET, which would later be known as the VMOS (V groove MOSFET). The same year, the DMOS (double diffused MOSFET) with self aligned gate was first reported by Y. Tarui, Y. Hayashi and Toshihiro Sekigawa of the Electrotechnical Laboratory (ETL). In 1974, Jun ichi Nishizawa at Tohoku University invented a power MOSFET for audio, which was soon manufactured by Yamaha Corporation for their high fidelity audio amplifiers. JVC, Pioneer Corporation, Sony and Toshiba also began manufacturing amplifiers with power MOSFETs in 1974. Siliconix commercially introduced a VMOS in 1975. and 4G. Alex Lidow co invented the HexFET, a hexagonal type of Power MOSFET, at Stanford University in 1977, along with Tom Herman. The HexFET was commercialized by International Rectifier in 1978. The superjunction MOSFET is a type of power MOSFET that uses P+ columns that penetrate the N− epitaxial layer. The idea of stacking P and N layers was first proposed by Shozo Shirota and Shigeo Kaneda at Osaka University in 1978. David J. Coe at Philips invented the superjunction MOSFET with alternating p type and n type layers by filing a US patent in 1984 which was awarded in 1988.

The power MOSFET is the most widely used power semiconductor device in the world. as of 2018, over 50 billion power MOSFETs are shipped annually. These include the trench power MOSFET, which sold over 100 billion units up until February 2017, and STMicroelectronics' MDmesh (superjunction MOSFET) which has sold 5 billion units as of 2019. RF DMOS, also known as RF power MOSFET, is a type of DMOS power transistor designed for radio frequency (RF) applications. It is used in various radio and RF applications. Power MOSFETs are widely used in transportation technology, which include a wide range of vehicles. In the automotive industry, power MOSFETs are widely used in automotive electronics. where is the permittivity of the Silicon, q is the electron charge, and N is the doping level. The value of CGDj can be approximated using the expression of the plane capacitor:

Where AGD is the surface area of the gate drain overlap. Therefore, it comes:

It can be seen that CGDj (and thus CGD) is a capacitance whose value is dependent upon the gate to drain voltage. As this voltage increases, the capacitance decreases. When the MOSFET is in on state, CGDj is shunted, so the gate to drain capacitance remains equal to CoxD, a constant value.

As the source metallization overlaps the P wells (see figure 1), the drain and source terminals are separated by a P N junction. Therefore, CDS is the junction capacitance. This is a non linear capacitance, and its value can be calculated using the same equation as for CGDj.

To operate, the MOSFET must be connected to the external circuit, most of the time using wire bonding (although alternative techniques are investigated). These connections exhibit a parasitic inductance, which is in no way specific to the MOSFET technology, but has important effects because of the high commutation speeds. Parasitic inductances tend to maintain their current constant and generate overvoltage during the transistor turn off, resulting in increasing commutation losses. A parasitic inductance can be associated with each terminal of the MOSFET. They have different effects:
the gate inductance has little influence (assuming it is lower than some hundreds of nanohenries), because the current gradients on the gate are relatively slow. In some cases, however, the gate inductance and the input capacitance of the transistor can constitute an oscillator. This must be avoided, as it results in very high commutation losses (up to the destruction of the device). On a typical design, parasitic inductances are kept low enough to prevent this phenomenon;
the drain inductance tends to reduce the drain voltage when the MOSFET turns on, so it reduces turn on losses. However, as it creates an overvoltage during turn off, it increases turn off losses;
the source parasitic inductance has the same behaviour as the drain inductance, plus a feedback effect that makes commutation last longer, thus increasing commutation losses. at the beginning of a fast turn on, due to the source inductance, the voltage at the source (on the die) will be able to jump up as well as the gate voltage; the internal VGS voltage will remain low for a longer time, therefore delaying turn on. at the beginning of a fast turn off, as current through the source inductance decreases sharply, the resulting voltage across it goes negative (with respect to the lead outside the package) raising the internal VGS voltage, keeping the MOSFET on, and therefore delaying turn off.

The gate oxide is very thin (100 nm or less), so it can only sustain a limited voltage. In the datasheets, manufacturers often state a maximum gate to source voltage, around 20 V, and exceeding this limit can result in destruction of the component. Furthermore, a high gate to source voltage reduces significantly the lifetime of the MOSFET, with little to no advantage on RDSon reduction. To deal with this issue, a gate driver circuit is often used.

Power MOSFETs have a maximum specified drain to source voltage (when turned off), beyond which breakdown may occur. Exceeding the breakdown voltage causes the device to conduct, potentially damaging it and other circuit elements due to excessive power dissipation.

The drain current must generally stay below a certain specified value (maximum continuous drain current). It can reach higher values for very short durations of time (maximum pulsed drain current, sometimes specified for various pulse durations). The drain current is limited by heating due to resistive losses in internal components such as bond wires, and other phenomena such as electromigration in the metal layer.

The junction temperature (TJ) of the MOSFET must stay under a specified maximum value for the device to function reliably, determined by MOSFET die layout and packaging materials. The packaging often limits the maximum junction temperature, due to the molding compound and (where used) epoxy characteristics. The maximum operating ambient temperature is determined by the power dissipation and thermal resistance. The junction to case thermal resistance is intrinsic to the device and package; the case to ambient thermal resistance is largely dependent on the board/mounting layout, heatsinking area and air/fluid flow. The type of power dissipation, whether continuous or pulsed, affects the maximum operating temperature, due to thermal mass characteristics; in general, the lower the frequency of pulses for a given power dissipation, the higher maximum operating ambient temperature, due to allowing a longer interval for the device to cool down. Models, such as a Foster network, can be used to analyze temperature dynamics from power transients.

The safe operating area defines the combined ranges of drain current and drain to source voltage the power MOSFET is able to handle without damage. It is represented graphically as an area in the plane defined by these two parameters. Both drain current and drain to source voltage must stay below their respective maximum values, but their product must also stay below the maximum power dissipation the device is able to handle. Thus, the device cannot be operated at its maximum current and maximum voltage simultaneously.

The equivalent circuit for a power MOSFET consists of one MOSFET in parallel with a parasitic BJT. If the BJT turns ON, it cannot be turned off, since the gate has no control over it. This phenomenon is known as "latch up", which can lead to device destruction. The BJT can be turned on due to a voltage drop across the p type body region. To avoid latch up, the body and the source are typically short circuited within the device package.

As described above, the current handling capability of a power MOSFET is determined by its gate channel width. The gate channel width is the third (Z axis) dimension of the cross sections pictured. To minimize cost and size, it is valuable to keep the transistor's die area size as small as possible. Therefore, optimizations have been developed to increase the width of the channel surface area, i. e., increase the "channel density". They mainly consist of creating cellular structures repeated over the whole area of the MOSFET die. Several shapes have been proposed for these cells, the most famous being the hexagonal shape used in International Rectifier's HEXFET devices. Another way to increase the channel density is to reduce the size of the elementary structure. This allows for more cells in a given surface area, and therefore more channel width. However, as the cell size shrinks, it becomes more difficult to ensure proper contact of every cell. To overcome this, a "strip" structure is often used (see figure). It is less efficient than a cellular structure of equivalent resolution in terms of channel density, but can cope with smaller pitch. Another advantage of the planar stripe structure is that it is less susceptible to failure during avalanche breakdown events in which the parasitic bipolar transistor turns on from sufficient forward bias. In the cellular structure, if the source terminal of any one cell is poorly contacted, then it becomes much more likely that the parasitic bipolar transistor latches on during an avalanche breakdown event. Because of this, MOSFETs utilizing a planar stripe structure can only fail during avalanche breakdown due to extreme thermal stress.

A P substrate MOSFET (often called PMOS) is a MOSFET with opposite doping types (N instead of P and P instead of N in the cross section in figure 1). This MOSFET is made using a P type substrate, with a P− epitaxy. As the channel sits in a N region, this transistor is turned on by a negative gate to source voltage. This makes it desirable in a buck converter, where one of the terminals of the switch is connected to the high side of the input voltage: with a N MOSFET, this configuration requires to apply to the gate a voltage equal to , whereas no voltage over is required with a P MOSFET. The main disadvantage of this type of MOSFET is the poor on state performance, as it uses holes as charge carriers, which have a much lower mobility than electrons. As resistivity is directly related to mobility, a given PMOS device will have a three times higher than a N MOSFET with the same dimensions.

The VMOS structure has a V groove at the gate region and was used for the first commercial devices.

In this power MOSFET structure, also called trench MOS, the gate electrode is buried in a trench etched in the silicon. This results in a vertical channel. The main interest of the structure is the absence of the JFET effect. The name of the structure comes from the U shape of the trench.

Especially for voltages beyond 500 V, some manufacturers, including Infineon Technologies with its CoolMOS products, have begun to use a charge compensation principle. With this technology, the resistance of the epitaxial layer, which is the biggest contributor (more than 95%) to the device resistance of high voltage MOSFETs, can be reduced by a factor of greater than 5. Seeking to improve the manufacturing efficiency and reliability of super junction MOSFETs, Renesas Electronics developed a super junction structure with a deep trench process technique. This technology entails etching trenches in the low impurity N type material to form P type regions. This process overcomes problems inherent to the multi level epitaxial growth approach and results in extremely low on resistance and reduced internal capacitance. Due to the increased p n junction area, a super junction structure has a smaller reverse recovery time but larger reverse recovery current compared to a conventional planar power MOSFET.