Микробағдарламаны басқару тізбегі және микросекуенцерлер

In computer architecture and engineering, a sequencer or microsequencer generates the addresses used to step through the microprogram of a control store. It is used as a part of the control unit of a CPU or as a stand alone generator for address ranges. Usually the addresses are generated by some combination of a counter, a field from a microinstruction, and some subset of the instruction register. A counter is used for the typical case, that the next microinstruction is the one to execute. A field from the microinstruction is used for jumps, or other logic. Since CPUs implement an instruction set, it's very useful to be able to decode the instruction's bits directly into the sequencer, to select a set of microinstructions to perform a CPU's instructions. Most modern CISC processors use a combination of pipelined logic to process lower complexity opcodes which can be completed in one clock cycle, and microcode to implement ones that take multiple clock cycles to complete. One of the first integrated microcoded processors was the IBM PALM Processor, which emulated all of the processor's instruction in microcode and was used on the IBM 5100, one of the first personal computers. Recent examples of similar open sourced microsequencer based processors are the MicroCore Labs MCL86, MCL51 , and MCL65 cores which emulate the Intel 8086/8088, 8051 and MOS 6502 instruction sets entirely in microcode.

The Digital Scientific Corp. Meta 4 Series 16 computer system was a user microprogrammable system first available in 1970. Branches in the microcode sequence occur in
one of three ways. A branch microinstruction specifies the address of the next instruction, either conditionally or unconditionally. The logical index (IX) option causes the 16 bit Link register to be logical ORed into the branch address, thus providing a simple indexed branch capability. All the arithmetic/logical instructions allow the jump (J) modifier, which redirects execution to the microinstruction addressed by the Link register. All the arithmetic/logical instructions allow both the decrement counter (D) and jump (J) modifiers. In this case, the 8 bit loop counter register is decremented. If it is then not zero, a branch is taken to the contents of the Link register. If it is zero, execution continues with the next instruction. One more sequencing option allowed on a branch instruction is the execute (XQ) option. When specified, the single instruction at the branch address is executed, but then execution continues after the original branch instruction. The IX option can be used with the XQ option.

This description has been simplified. It ignores the following features. The model 40 can run in CPU mode or channel mode. The description addresses only CPU mode. If the microinstruction is not in functional branch format and the CD field is 1 or 3, bit 1 of the next address is always 0. In this case, the values of the CD and CB fields determine one of a set of control lines to raise.