SystemVerilog

Hardware description and hardware verification language

SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since 2008, Verilog is now part of the same IEEE standard. It is commonly used in the semiconductor and electronic design industry as an evolution of Verilog.

SystemVerilog started with the donation of the Superlog language to Accellera in 2002 by the startup company Co Design Automation. The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800 2005. In 2009, the standard was merged with the base Verilog (IEEE 1364 2005) standard, creating IEEE Standard 1800 2009. The SystemVerilog standard was subsequently updated in 2012, 2017, and most recently in December 2023.

There are two types of data lifetime specified in SystemVerilog: static and automatic. Automatic variables are created the moment program execution comes to the scope of the variable. Static variables are created at the start of the program's execution and keep the same value during the entire program's lifespan, unless assigned a new value during execution. Any variable that is declared inside a task or function without specifying type will be considered automatic. To specify that a variable is static place the "static" keyword in the declaration before the type, e. g., "static int x;". The "automatic" keyword is used in the same way.

The following verification features are typically not synthesizable, meaning they cannot be implemented in hardware based on HDL code. Instead, they assist in the creation of extensible, flexible test benches.

A complex test environment consists of reusable verification components that must communicate with one another. Verilog's 'event' primitive allowed different blocks of procedural statements to trigger each other, but enforcing thread synchronization was up to the programmer's (clever) usage. SystemVerilog offers two primitives specifically for interthread synchronization: mailbox and semaphore. The mailbox is modeled as a FIFO message queue. Optionally, the FIFO can be type parameterized so that only objects of the specified type may be passed through it. Typically, objects are class instances representing transactions: elementary operations (for example, sending a frame) that are executed by the verification components. The semaphore is modeled as a counting semaphore.

In addition to the new features above, SystemVerilog enhances the usability of Verilog's existing language features. The following are some of these enhancements:

The procedural assignment operators (<=, =) can now operate directly on arrays. Port (inout, input, output) definitions are now expanded to support a wider variety of data types: struct, enum, real, and multi dimensional types are supported. The for loop construct now allows automatic variable declaration inside the for statement. Loop flow control is improved by the continue and break statements. SystemVerilog adds a do/while loop to the while loop construct. Constant variables, i. e. those designated as non changing during runtime, can be designated by use of const. Variable initialization can now operate on arrays. Increment and decrement operators (x++, ++x, x , x) are supported in SystemVerilog, as are other compound assignment operators (x += a, x = a, x *= a, x /= a, x %= a, x <<= a, x >>= a, x &= a, x ^= a, x |= a) as in C and descendants. The preprocessor has improved `define macro substitution capabilities, specifically substitution within literal strings (""), as well as concatenation of multiple macro tokens into a single word. The fork/join construct has been expanded with join none and join any. Additions to the `timescale directive allow simulation timescale to be controlled more predictably in a large simulation environment, with each source file using a local timescale. Task ports can now be declared ref. A reference gives the task body direct access to the source arguments in the caller's scope, known as "pass by reference" in computer programming. Since it is operating on the original variable itself, rather than a copy of the argument's value, the task/function can modify variables (but not nets) in the caller's scope in real time. The inout/output port declarations pass variables by value, and defer updating the caller scope variable until the moment the task exits. Functions can now be declared void, which means it returns no value. Parameters can be declared any type, including user defined typedefs. Besides this, SystemVerilog allows convenient interface to foreign languages (like C/C++), by SystemVerilog DPI (Direct Programming Interface).

In the design verification role, SystemVerilog is widely used in the chip design industry. The three largest EDA vendors (Cadence Design Systems, Mentor Graphics, Synopsys) have incorporated SystemVerilog into their mixed language HDL simulators. Although no simulator can yet claim support for the entire SystemVerilog Language Reference Manual, making testbench interoperability a challenge, efforts to promote cross vendor compatibility are underway. In 2008, Cadence and Mentor released the Open Verification Methodology, an open source class library and usage framework to facilitate the development of re usable testbenches and canned verification IP. Synopsys, which had been the first to publish a SystemVerilog class library (VMM), subsequently responded by opening its proprietary VMM to the general public. Many third party providers have announced or already released SystemVerilog verification IP. In the design synthesis role (transformation of a hardware design description into a gate netlist), SystemVerilog adoption has been slow. Many design teams use design flows which involve multiple tools from different vendors. Most design teams cannot migrate to SystemVerilog RTL design until their entire front end tool suite (linters, formal verification and automated test structure generators) support a common language subset.