Intel x86 процессорларында жад сегментациясының іске асырылуы

Implementation of memory segmentation on Intel x86

x86 memory segmentation refers to the implementation of memory segmentation in the Intel x86 computer instruction set architecture. Segmentation was introduced on the Intel 8086 in 1978 as a way to allow programs to address more than 64 KB (65,536 bytes) of memory. The Intel 80286 introduced a second version of segmentation in 1982 that added support for virtual memory and memory protection. At this point the original mode was renamed to real mode, and the new version was named protected mode. The x86 64 architecture, introduced in 2003, has largely dropped support for segmentation in 64 bit mode. In both real and protected modes, the system uses 16 bit segment registers to derive the actual memory address. In real mode, the registers CS, DS, SS, and ES point to the currently used program code segment (CS), the current data segment (DS), the current stack segment (SS), and one extra segment determined by the programmer (ES). The Intel 80386, introduced in 1985, adds two additional segment registers, FS and GS, with no specific uses defined by the hardware. The way in which the segment registers are used differs between the two modes.

The 80286's protected mode extends the processor's address space to 224 bytes (16 megabytes), but not by adjusting the shift value. Instead, the 16 bit segment registers now contain an index into a table of segment descriptors containing 24 bit base addresses to which the offset is added. To support old software, the processor starts up in "real mode", a mode in which it uses the segmented addressing model of the 8086. There is a small difference though: the resulting physical address is no longer truncated to 20 bits, so real mode pointers (but not 8086 pointers) can now refer to addresses between 10000016 and 10FFEF16. This roughly 64 kilobyte region of memory was known as the High Memory Area (HMA), and later versions of DOS could use it to increase the available "conventional" memory (i. e. within the first MB). With the addition of the HMA, the total address space is approximately 1.06 MB. Though the 80286 does not truncate real mode addresses to 20 bits, a system containing an 80286 can do so with hardware external to the processor, by gating off the 21st address line, the A20 line. The IBM PC AT provided the hardware to do this (for full backward compatibility with software for the original IBM PC and PC/XT models), and so all subsequent "AT class" PC clones did as well. 286 protected mode was seldom used as it would have excluded the large body of users with 8086/88 machines. Moreover, it still necessitated dividing memory into 64k segments like was done in real mode. This limitation can be worked around on 32 bit CPUs which permit the use of memory pointers greater than 64k in size, however as the Segment Limit field is only 24 bit long, the maximum segment size that can be created is 16MB (although paging can be used to allocate more memory, no individual segment may exceed 16MB). This method was commonly used on Windows 3. x applications to produce a flat memory space, although as the OS itself was still 16 bit, API calls could not be made with 32 bit instructions. Thus, it was still necessary to place all code that performs API calls in 64k segments. Once 286 protected mode is invoked, it could not be exited except by performing a hardware reset. Machines following the rising IBM PC/AT standard could feign a reset to the CPU via the standardised keyboard controller, but this was significantly sluggish. Windows 3. x worked around both of these problems by intentionally triggering a triple fault in the interrupt handling mechanisms of the CPU, which would cause the CPU to drop back into real mode, nearly instantly.

In the Intel 80386 and later, protected mode retains the segmentation mechanism of 80286 protected mode, but a paging unit has been added as a second layer of address translation between the segmentation unit and the physical bus. Also, importantly, address offsets are 32 bit (instead of 16 bit), and the segment base in each segment descriptor is also 32 bit (instead of 24 bit). The general operation of the segmentation unit is otherwise unchanged. The paging unit may be enabled or disabled; if disabled, operation is the same as on the 80286. If the paging unit is enabled, addresses in a segment are now virtual addresses, rather than physical addresses as they were on the 80286. That is, the segment starting address, the offset, and the final 32 bit address the segmentation unit derived by adding the two are all virtual (or logical) addresses when the paging unit is enabled. When the segmentation unit generates and validates these 32 bit virtual addresses, the enabled paging unit finally translates these virtual addresses into physical addresses. The physical addresses are 32 bit on the 386, but can be larger on newer processors which support Physical Address Extension. The 80386 also introduced two new general purpose data segment registers, FS and GS, to the original set of four segment registers (CS, DS, ES, and SS). A 386 CPU can be put back into real mode by clearing a bit in the CR0 control register, however this is a privileged operation in order to enforce security and robustness. By way of comparison, a 286 could only be returned to real mode by forcing a processor reset, e. g. by a triple fault or using external hardware.

The x86 64 architecture does not use segmentation in long mode (64 bit mode). Four of the segment registers, CS, SS, DS, and ES, are forced to base address 0, and the limit to 264. The segment registers FS and GS can still have a nonzero base address. This allows operating systems to use these segments for special purposes. Unlike the global descriptor table mechanism used by legacy modes, the base address of these segments is stored in a model specific register. The x86 64 architecture further provides the special SWAPGS instruction, which allows swapping the kernel mode and user mode base addresses. For instance, Microsoft Windows on x86 64 uses the GS segment to point to the Thread Environment Block, a small data structure for each thread, which contains information about exception handling, thread local variables, and other per thread state. Similarly, the Linux kernel uses the GS segment to store per CPU data. GS/FS are also used in gcc's thread local storage and canary based stack protector.