x86-64 архитектурасы және оның мүмкіндіктері

64 bit version of x86 architecture

x86 64 (also known as x64, x86 64, AMD64, and Intel 64) is a 64 bit version of the x86 instruction set, first announced in 1999. It introduced two new modes of operation, 64 bit mode and compatibility mode, along with a new 4 level paging mode. With 64 bit mode and the new paging mode, it supports vastly larger amounts of virtual memory and physical memory than was possible on its 32 bit predecessors, allowing programs to store larger amounts of data in memory. x86 64 also expands general purpose registers to 64 bit, and expands the number of them from 8 (some of which had limited or fixed functionality, e. g. for stack management) to 16 (fully general), and provides numerous other enhancements. Floating point arithmetic is supported via mandatory SSE2 like instructions, and x87/MMX style registers are generally not used (but still available even in 64 bit mode); instead, a set of 16 vector registers, 128 bits each, is used. (Each register can store one or two double precision numbers or one to four single precision numbers, or various integer formats.) In 64 bit mode, instructions are modified to support 64 bit operands and 64 bit addressing mode. The compatibility mode defined in the architecture allows 16 bit and 32 bit user applications to run unmodified, coexisting with 64 bit applications if the 64 bit operating system supports them. As the full x86 16 bit and 32 bit instruction sets remain implemented in hardware without any intervening emulation, these older executables can run with little or no performance penalty, while newer or modified applications can take advantage of new features of the processor design to achieve performance improvements. Also, a processor supporting x86 64 still powers on in real mode for full backward compatibility with the 8086, as x86 processors supporting protected mode have done since the 80286. The original specification, created by AMD and released in 2000, has been implemented by AMD, Intel, and VIA. The AMD K8 microarchitecture, in the Opteron and Athlon 64 processors, was the first to implement it. This was the first significant addition to the x86 architecture designed by a company other than Intel. Intel was forced to follow suit and introduced a modified NetBurst family which was software compatible with AMD's specification. VIA Technologies introduced x86 64 in their VIA Isaiah architecture, with the VIA Nano. The x86 64 architecture was quickly adopted for desktop and laptop personal computers and servers which were commonly configured for 16 GiB (gibibytes) of memory or more. It has effectively replaced the discontinued Intel Itanium architecture (formerly IA 64), which was originally intended to replace the x86 architecture. x86 64 and Itanium are not compatible on the native instruction set level, and operating systems and applications compiled for one architecture cannot be run on the other natively.

AMD64 (also variously referred to by AMD in their literature and documentation as “AMD 64 bit Technology” and “AMD x86 64 Architecture”) was created as an alternative to the radically different IA 64 architecture designed by Intel and Hewlett Packard, which was backward incompatible with IA 32, the 32 bit version of the x86 architecture. AMD originally announced AMD64 in 1999 with a full specification available in August 2000. As AMD was never invited to be a contributing party for the IA 64 architecture and any kind of licensing seemed unlikely, the AMD64 architecture was positioned by AMD from the beginning as an evolutionary way to add 64 bit computing capabilities to the existing x86 architecture while supporting legacy 32 bit x86 code, as opposed to Intel's approach of creating an entirely new, completely x86 incompatible 64 bit architecture with IA 64. The first AMD64 based processor, the Opteron, was released in April 2003.

AMD's processors implementing the AMD64 architecture include Opteron, Athlon 64, Athlon 64 X2, Athlon 64 FX, Athlon II (followed by "X2", "X3", or "X4" to indicate the number of cores, and XLT models), Turion 64, Turion 64 X2, Sempron ("Palermo" E6 stepping and all "Manila" models), Phenom (followed by "X3" or "X4" to indicate the number of cores), Phenom II (followed by "X2", "X3", "X4" or "X6" to indicate the number of cores), FX, Fusion/APU and Ryzen/Epyc.

The operating system can also limit the virtual address space. Details, where applicable, are given in the "Operating system compatibility and characteristics" section.

Current AMD64 processors support a physical address space of up to 248 bytes of RAM, or 256 TiB. The operating system may place additional limits on the amount of RAM that is usable or supported. Details on this point are given in the "Operating system compatibility and characteristics" section of this article.

Long mode is the architecture's intended primary mode of operation; it is a combination of the processor's native 64 bit mode and a combined 32 bit and 16 bit compatibility mode. It is used by 64 bit operating systems. Under a 64 bit operating system, 64 bit programs run under 64 bit mode, and 32 bit and 16 bit protected mode applications (that do not need to use either real mode or virtual 8086 mode in order to execute at any time) run under compatibility mode. Real mode programs and programs that use virtual 8086 mode at any time cannot be run in long mode unless those modes are emulated in software. (after the Yamhill River in Oregon's Willamette Valley). After several years of denying its existence, Intel announced at the February 2004 IDF that the project was indeed underway. Intel's chairman at the time, Craig Barrett, admitted that this was one of their worst kept secrets. Intel's name for this instruction set has changed several times. The name used at the IDF was CT (presumably for Clackamas Technology, another codename from an Oregon river); within weeks they began referring to it as IA 32e (for IA 32 extensions) and in March 2004 unveiled the "official" name EM64T (Extended Memory 64 Technology). In late 2006 Intel began instead using the name Intel 64 for its implementation, paralleling AMD's use of the name AMD64. The first processor to implement Intel 64 was the multi socket processor Xeon code named Nocona in June 2004. In contrast, the initial Prescott chips (February 2004) did not enable this feature. Intel subsequently began selling Intel 64 enabled Pentium 4s using the E0 revision of the Prescott core, being sold on the OEM market as the Pentium 4, model F. The E0 revision also adds eXecute Disable (XD) (Intel's name for the NX bit) to Intel 64, and has been included in then current Xeon code named Irwindale. Intel's official launch of Intel 64 (under the name EM64T at that time) in mainstream desktop processors was the N0 stepping Prescott 2M. The first Intel mobile processor implementing Intel 64 is the Merom version of the Core 2 processor, which was released on July 27, 2006. None of Intel's earlier notebook CPUs (Core Duo, Pentium M, Celeron M, Mobile Pentium 4) implement Intel 64.

Intel's processors implementing the Intel64 architecture include the Pentium 4 F series/5x1 series, 506, and 516, Celeron D models 3x1, 3x6, 355, 347, 352, 360, and 365 and all later Celerons, all models of Xeon since "Nocona", all models of Pentium Dual Core processors since "Merom 2M", the Atom 230, 330, D410, D425, D510, D525, N450, N455, N470, N475, N550, N570, N2600 and N2800, all versions of the Pentium D, Pentium Extreme Edition, Core 2, Core i9, Core i7, Core i5, and Core i3 processors, and the Xeon Phi 7200 series processors.

Although nearly identical, there are some differences between the two instruction sets in the semantics of a few seldom used machine instructions (or situations), which are mainly used for system programming. Compilers generally produce executables (i. e. machine code) that avoid any differences, at least for ordinary application programs. This is therefore of interest mainly to developers of compilers, operating systems and similar, which must deal with individual and special system instructions.

The AMD64 processors prior to Revision F (distinguished by the switch from DDR to DDR2 memory and new sockets AM2, F and S1) of 2006 lacked the CMPXCHG16B instruction, which is an extension of the CMPXCHG8B instruction present on most post 80486 processors. Similar to CMPXCHG8B, CMPXCHG16B allows for atomic operations on octa words (128 bit values). This is useful for parallel algorithms that use compare and swap on data larger than the size of a pointer, common in lock free and wait free algorithms. Without CMPXCHG16B one must use workarounds, such as a critical section or alternative lock free approaches. Its absence also prevents 64 bit Windows prior to Windows 8.1 from having a user mode address space larger than 8 TiB. The 64 bit version of Windows 8.1 requires the instruction. Early AMD64 and Intel 64 CPUs lacked LAHF and SAHF instructions in 64 bit mode. AMD introduced these instructions (also in 64 bit mode) with their 90 nm (revision D) processors, starting with Athlon 64 in October 2004. Intel introduced the instructions in October 2005 with the 0F47h and later revisions of NetBurst. The 64 bit version of Windows 8.1 requires this feature. This feature is required by all versions of Windows 8. Early Intel 64 implementations had a 36 bit (64 GiB) physical addressing of memory while original AMD64 implementations had a 40 bit (1 TiB) physical addressing. Intel used the 40 bit physical addressing first on Xeon MP (Potomac), launched on 29 March 2005. The difference is not a difference of the user visible ISAs. In 2007 AMD 10h based Opteron was the first to provide a 48 bit (256 TiB) physical address space. Intel 64's physical addressing was extended to 44 bits (16 TiB) in Nehalem EX in 2010 and to 46 bits (64 TiB) in Sandy Bridge E in 2011. With the Ice Lake 3rd gen Xeon Scalable processors, Intel increased the virtual addressing to 57 bits (128 PiB) and physical to 52 bits (4 PiB) in 2021, necessitating a 5 level paging. The following year AMD64 added the same in 4th generation EPYC (Genoa). Non server CPUs retain smaller address spaces for longer.

In supercomputers tracked by TOP500, the appearance of 64 bit extensions for the x86 architecture enabled 64 bit x86 processors by AMD and Intel to replace most RISC processor architectures previously used in such systems (including PA RISC, SPARC, Alpha and others), as well as 32 bit x86, even though Intel itself initially tried unsuccessfully to replace x86 with a new incompatible 64 bit architecture in the Itanium processor. as of 2023, a HPE EPYC based supercomputer called Frontier is number one. The first ARM based supercomputer appeared on the list in 2018 and, in recent years, non CPU architecture co processors (GPGPU) have also played a big role in performance. Intel's Xeon Phi "Knights Corner" coprocessors, which implement a subset of x86 64 with some vector extensions, are also used, along with x86 64 processors, in the Tianhe 2 supercomputer.

The following operating systems and releases support the x86 64 architecture in long mode.

Preliminary infrastructure work was started in February 2004 for a x86 64 port. This development later stalled. Development started again during July 2007
and continued during Google Summer of Code 2008 and SoC 2009. The first official release to contain x86 64 support was version 2.4.

FreeBSD first added x86 64 support under the name "amd64" as an experimental architecture in 5.1 RELEASE in June 2003. It was included as a standard distribution architecture as of 5.2 RELEASE in January 2004. Since then, FreeBSD has designated it as a Tier 1 platform. The 6.0 RELEASE version cleaned up some quirks with running x86 executables under amd64, and most drivers work just as they do on the x86 architecture. Work is currently being done to integrate more fully the x86 application binary interface (ABI), in the same manner as the Linux 32 bit ABI compatibility currently works.

x86 64 architecture support was first committed to the NetBSD source tree on June 19, 2001. As of NetBSD 2.0, released on December 9, 2004, NetBSD/amd64 is a fully integrated and supported port. 32 bit code is still supported in 64 bit mode, with a netbsd 32 kernel compatibility layer for 32 bit syscalls. The NX bit is used to provide non executable stack and heap with per page granularity (segment granularity being used on 32 bit x86).

OpenBSD has supported AMD64 since OpenBSD 3.5, released on May 1, 2004. Complete in tree implementation of AMD64 support was achieved prior to the hardware's initial release because AMD had loaned several machines for the project's hackathon that year. OpenBSD developers have taken to the platform because of its support for the NX bit, which allowed for an easy implementation of the W^X feature. The code for the AMD64 port of OpenBSD also runs on Intel 64 processors which contains cloned use of the AMD64 extensions, but since Intel left out the page table NX bit in early Intel 64 processors, there is no W^X capability on those Intel CPUs; later Intel 64 processors added the NX bit under the name "XD bit". Symmetric multiprocessing (SMP) works on OpenBSD's AMD64 port, starting with release 3.6 on November 1, 2004.

It is possible to enter long mode under DOS without a DOS extender, but the user must return to real mode in order to call BIOS or DOS interrupts. It may also be possible to enter long mode with a DOS extender similar to DOS/4GW, but more complex since x86 64 lacks virtual 8086 mode. DOS itself is not aware of that, and no benefits should be expected unless running DOS in an emulation with an adequate virtualization driver backend, for example: the mass storage interface.

Linux was the first operating system kernel to run the x86 64 architecture in long mode, starting with the 2.4 version in 2001 (preceding the hardware's availability). Linux also provides backward compatibility for running 32 bit executables. This permits programs to be recompiled into long mode while retaining the use of 32 bit programs. Current Linux distributions ship with x86 64 native kernels and userlands. Some, such as Arch Linux, SUSE, Mandriva, and Debian, allow users to install a set of 32 bit components and libraries when installing off a 64 bit distribution medium, thus allowing most existing 32 bit applications to run alongside the 64 bit OS. x32 ABI (Application Binary Interface), introduced in Linux 3.4, allows programs compiled for the x32 ABI to run in the 64 bit mode of x86 64 while only using 32 bit pointers and data fields. Though this limits the program to a virtual address space of 4 GiB it also decreases the memory footprint of the program and in some cases can allow it to run faster. or up to 128 PiB (virtual) and 4 PiB (physical) with 5 level paging enabled.

Mac OS X 10.4.7 and higher versions of Mac OS X 10.4 run 64 bit command line tools using the POSIX and math libraries on 64 bit Intel based machines, just as all versions of Mac OS X 10.4 and 10.5 run them on 64 bit PowerPC machines. No other libraries or frameworks work with 64 bit applications in Mac OS X 10.4. The kernel, and all kernel extensions, are 32 bit only. Mac OS X 10.5 supports 64 bit GUI applications using Cocoa, Quartz, OpenGL, and X11 on 64 bit Intel based machines, as well as on 64 bit PowerPC machines. All non GUI libraries and frameworks also support 64 bit applications on those platforms. The kernel, and all kernel extensions, are 32 bit only. Mac OS X 10.6 is the first version of macOS that supports a 64 bit kernel. However, not all 64 bit computers can run the 64 bit kernel, and not all 64 bit computers that can run the 64 bit kernel will do so by default. The 64 bit kernel, like the 32 bit kernel, supports 32 bit applications; both kernels also support 64 bit applications. 32 bit applications have a virtual address space limit of 4 GiB under either kernel. The 64 bit kernel does not support 32 bit kernel extensions, and the 32 bit kernel does not support 64 bit kernel extensions. OS X 10.8 includes only the 64 bit kernel, but continues to support 32 bit applications; it does not support 32 bit kernel extensions, however. macOS 10.15 includes only the 64 bit kernel and no longer supports 32 bit applications. This removal of support has presented a problem for WineHQ (and the commercial version CrossOver), as it needs to still be able to run 32 bit Windows applications. The solution, termed wine32on64, was to add thunks that bring the CPU in and out of 32 bit compatibility mode in the nominally 64 bit application. macOS uses the universal binary format to package 32 and 64 bit versions of application and library code into a single file; the most appropriate version is automatically selected at load time. In Mac OS X 10.6, the universal binary format is also used for the kernel and for those kernel extensions that support both 32 bit and 64 bit kernels.

Solaris 10 and later releases support the x86 64 architecture. For Solaris 10, just as with the SPARC architecture, there is only one operating system image, which contains a 32 bit kernel and a 64 bit kernel; this is labeled as the "x64/x86" DVD ROM image. The default behavior is to boot a 64 bit kernel, allowing both 64 bit and existing or new 32 bit executables to be run. A 32 bit kernel can also be manually selected, in which case only 32 bit executables will run. The isainfo command can be used to determine if a system is running a 64 bit kernel. For Solaris 11, only the 64 bit kernel is provided. However, the 64 bit kernel supports both 32 and 64 bit executables, libraries, and system calls.

x64 editions of Microsoft Windows client and server—Windows XP Professional x64 Edition and Windows Server 2003 x64 Edition—were released in March 2005. Internally they are actually the same build (5.2.3790.1830 SP1), as they share the same source base and operating system binaries, so even system updates are released in unified packages, much in the manner as Windows 2000 Professional and Server editions for x86. Windows Vista, which also has many different editions, was released in January 2007. Windows 7 was released in July 2009. Windows Server 2008 R2 was sold in only x64 and Itanium editions; later versions of Windows Server only offer an x64 edition. Versions of Windows for x64 prior to Windows 8.1 and Windows Server 2012 R2 offer the following:
8 TiB of virtual address space per process, accessible from both user mode and kernel mode, referred to as the user mode address space. An x64 program can use all of this, subject to backing store limits on the system, and provided it is linked with the "large address aware" option, which is present by default. This is a 4096 fold increase over the default 2 GiB user mode virtual address space offered by 32 bit Windows. 8 TiB of kernel mode virtual address space for the operating system. Under Windows 8.1 and Windows Server 2012 R2, both user mode and kernel mode virtual address spaces have been extended to 128 TiB. Unlike the use of the /3GiB boot option on x86, this does not reduce the kernel mode virtual address space available to the operating system. 32 bit applications can, therefore, benefit from running on x64 Windows even if they are not recompiled for x86 64. Both 32 and 64 bit applications, if not linked with "large address aware", are limited to 2 GiB of virtual address space. Ability to use up to 128 GiB (Windows XP/Vista), 192 GiB (Windows 7), 512 GiB (Windows 8), 1 TiB (Windows Server 2003), 2 TiB (Windows Server 2008/Windows 10), 4 TiB (Windows Server 2012), or 24 TiB (Windows Server 2016/2019) of physical random access memory (RAM). LLP64 data model: in C/C++, "int" and "long" types are 32 bits wide, "long long" is 64 bits, while pointers and types derived from pointers are 64 bits wide. Kernel mode device drivers must be 64 bit versions; there is no way to run 32 bit kernel mode executables within the 64 bit operating system. User mode device drivers can be either 32 bit or 64 bit. 16 bit Windows (Win16) and DOS applications will not run on x86 64 versions of Windows due to the removal of the virtual DOS machine subsystem (NTVDM) which relied upon the ability to use virtual 8086 mode. Virtual 8086 mode cannot be entered while running in long mode. Full implementation of the NX (No Execute) page protection feature. This is also implemented on recent 32 bit versions of Windows when they are started in PAE mode. Instead of FS segment descriptor on x86 versions of the Windows NT family, GS segment descriptor is used to point to two operating system defined structures: Thread Information Block (NT TIB) in user mode and Processor Control Region (KPCR) in kernel mode. Thus, for example, in user mode GS:0 is the address of the first member of the Thread Information Block. Maintaining this convention made the x86 64 port easier, but required AMD to retain the function of the FS and GS segments in long mode – even though segmented addressing per se is not really used by any modern operating system. which are also supported on Intel processors as of Broadwell.) Some components like Jet Database Engine and Data Access Objects will not be ported to 64 bit architectures such as x86 64 and IA 64. Microsoft Visual Studio can compile native applications to target either the x86 64 architecture, which can run only on 64 bit Microsoft Windows, or the IA 32 architecture, which can run as a 32 bit application on 32 bit Microsoft Windows or 64 bit Microsoft Windows in WoW64 emulation mode. Managed applications can be compiled either in IA 32, x86 64 or AnyCPU modes. Software created in the first two modes behave like their IA 32 or x86 64 native code counterparts respectively; When using the AnyCPU mode, however, applications in 32 bit versions of Microsoft Windows run as 32 bit applications, while they run as a 64 bit application in 64 bit editions of Microsoft Windows.

Both the PlayStation 4 and Xbox One, and all variants of those consoles, incorporate AMD x86 64 processors, based on the Jaguar microarchitecture. Firmware and games are written in x86 64 code; no legacy x86 code is involved. The current generation, the PlayStation 5 and the Xbox Series X and Series S respectively, also incorporate AMD x86 64 processors, based on the Zen 2 microarchitecture. Although considered a PC, the Steam Deck uses a custom AMD x86 64 accelerated processing unit (APU), based on the Zen 2 microarchitecture.