Архитектура набора команд IA-64 (Intel Itanium)

Microprocessor instruction set architecture

IA 64 (Intel Itanium architecture) is the instruction set architecture (ISA) of the discontinued Itanium family of 64 bit Intel microprocessors. The basic ISA specification originated at Hewlett Packard (HP), and was subsequently implemented by Intel in collaboration with HP. The first Itanium processor, codenamed Merced, was released in 2001. The Itanium architecture is based on explicit instruction level parallelism, in which the compiler decides which instructions to execute in parallel. This contrasts with superscalar architectures, which depend on the processor to manage instruction dependencies at runtime. In all Itanium models, up to and including Tukwila, cores execute up to six instructions per clock cycle. In 2008, Itanium was the fourth most deployed microprocessor architecture for enterprise class systems, behind x86 64, Power ISA, and SPARC. In 2019, Intel announced the discontinuation of the last of the CPUs supporting the IA 64 architecture.

In 1989, HP began to become concerned that reduced instruction set computing (RISC) architectures were approaching a processing limit at one instruction per cycle. Both Intel and HP researchers had been exploring computer architecture options for future designs and separately began investigating a new concept known as very long instruction word (VLIW) which came out of research by Yale University in the early 1980s. VLIW is a computer architecture concept (like RISC and CISC) where a single instruction word contains multiple instructions encoded in one very long instruction word to facilitate the processor executing multiple instructions in each clock cycle. Typical VLIW implementations rely heavily on sophisticated compilers to determine at compile time which instructions can be executed at the same time and the proper scheduling of these instructions for execution and also to help predict the direction of branch operations. The value of this approach is to do more useful work in fewer clock cycles and to simplify processor instruction scheduling and branch prediction hardware requirements, with a penalty in increased processor complexity, cost, and energy consumption in exchange for faster execution.

During this time, HP had begun to believe that it was no longer cost effective for individual enterprise systems companies such as itself to develop proprietary microprocessors. Intel had also been researching several architectural options for going beyond the x86 ISA to address high end enterprise server and high performance computing (HPC) requirements. Intel and HP partnered in 1994 to develop the IA 64 ISA, using a variation of VLIW design concepts which Intel named explicitly parallel instruction computing (EPIC). Intel's goal was to leverage the expertise HP had developed in their early VLIW work along with their own to develop a volume product line targeted at the aforementioned high end systems that could be sold to all original equipment manufacturers (OEMs), while HP wished to be able to purchase off the shelf processors built using Intel's volume manufacturing and contemporary process technology that were better than their PA RISC processors. Intel took the lead on the design and commercialization process, while HP contributed to the ISA definition, the Merced/Itanium microarchitecture, and Itanium 2. The original goal year for delivering the first Itanium family product, Merced, was 1998. Compaq and Silicon Graphics decided to abandon further development of the Alpha and MIPS architectures respectively in favor of migrating to IA 64. By 1997, it was apparent that the IA 64 architecture and the compiler were much more difficult to implement than originally thought, and the delivery of Itanium began slipping. Since Itanium was the first ever EPIC processor, the development effort encountered more unanticipated problems than the team was accustomed to. In addition, the EPIC concept depended on compiler capabilities that had never been implemented before, so more research was needed. Several groups developed operating systems for the architecture, including Microsoft Windows, Unix and Unix like systems such as Linux, HP UX, FreeBSD, Solaris, Tru64 UNIX, (the last three were canceled before reaching the market). In 1999, Intel led the formation of an open source industry consortium to port Linux to IA 64 they named "Trillium" (and later renamed "Trillian" due to a trademark issue), which was led by Intel and included Caldera Systems, CERN, Cygnus Solutions, Hewlett Packard, IBM, Red Hat, SGI, SuSE, TurboLinux and VA Linux Systems. As a result, a working IA 64 Linux was delivered ahead of schedule and was the first OS to run on the new Itanium processors. Intel announced the official name of the processor, Itanium, on October 4, 1999. Within hours, the name Itanic had been coined on a Usenet newsgroup as a pun on the name Titanic, the "unsinkable" ocean liner that sank on its maiden voyage in 1912. The very next day on 5th October 1999, AMD announced their plans to extend Intel's x86 instruction set to include a fully downward compatible 64 bit mode, additionally revealing AMD's newly coming x86 64 bit architecture, which the company had already worked on, to be incorporated into AMD's upcoming eighth generation microprocessor, code named SledgeHammer. AMD also signaled a full disclosure of the architecture's specifications and further details to be available in August 2000. As AMD was never invited to be a contributing party for the IA 64 architecture and any kind of licensing seemed unlikely, AMD's AMD64 architecture extension was positioned from the beginning as an evolutionary way to add 64 bit computing capabilities to the existing x86 architecture, while still supporting legacy 32 bit x86 code, as opposed to Intel's approach of creating an entirely new, completely x86 incompatible 64 bit architecture with IA 64.

In January 2019, Intel announced that Kittson would be discontinued, with a last order date of January 2020, and a last ship date of July 2021. In November 2023, IA 64 support was removed from the Linux kernel.

From 2002 to 2006, Itanium 2 processors shared a common cache hierarchy. They had 16 KB of Level 1 instruction cache and 16 KB of Level 1 data cache. The L2 cache was unified (both instruction and data) and is 256 KB. The Level 3 cache was also unified and varied in size from 1.5 MB to 24 MB. The 256 KB L2 cache contains sufficient logic to handle semaphore operations without disturbing the main arithmetic logic unit (ALU). Main memory is accessed through a bus to an off chip chipset. The Itanium 2 bus was initially called the McKinley bus, but is now usually referred to as the Itanium bus. The speed of the bus has increased steadily with new processor releases. The bus transfers 2×128 bits per clock cycle, so the 200 MHz McKinley bus transferred 6.4 GB/s, and the 533 MHz Montecito bus transfers 17.056 GB/s