PowerPC: Архитектура RISC от альянса AIM

RISC instruction set architecture by AIM alliance

PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple–IBM–Motorola alliance, known as AIM. PowerPC, as an evolving instruction set, has been named Power ISA since 2006, while the old name lives on as a trademark for some implementations of Power Architecture–based processors. Originally intended for personal computers, the architecture is well known for being used by Apple's desktop and laptop lines from 1994 until 2006, and in several videogame consoles including Microsoft's Xbox 360, Sony's PlayStation 3, and Nintendo's GameCube, Wii, and Wii U. PowerPC was also used for the Curiosity and Perseverance rovers on Mars and a variety of satellites. It has since become a niche architecture for personal computers, particularly with AmigaOS 4 implementations, but remains popular for embedded systems. PowerPC was the cornerstone of AIM's PReP and Common Hardware Reference Platform (CHRP) initiatives in the 1990s. It is largely based on the earlier IBM POWER architecture, and retains a high level of compatibility with it; the architectures have remained close enough that the same programs and operating systems will run on both if some care is taken in preparation; newer chips in the Power series use the Power ISA.

The history of RISC began with IBM's 801 research project, on which John Cocke was the lead developer, where he developed the concepts of RISC in 1975–78. 801 based microprocessors were used in a number of IBM embedded products, eventually becoming the 16 register IBM ROMP processor used in the IBM RT PC. The RT PC was a rapid design implementing the RISC architecture. Between the years of 1982 and 1984, IBM started a project to build the fastest microprocessor on the market; this new 32 bit architecture became referred to as the America Project throughout its development cycle, which lasted for approximately 5–6 years. The result is the POWER instruction set architecture, introduced with the RISC System/6000 in early 1990. The original POWER microprocessor, one of the first superscalar RISC implementations, is a high performance, multi chip design. IBM soon realized that a single chip microprocessor was needed in order to scale its RS/6000 line from lower end to high end machines. Work began on a one chip POWER microprocessor, designated the RSC (RISC Single Chip). In early 1991, IBM realized its design could potentially become a high volume microprocessor used across the industry.

Most PowerPC chips switch endianness via a bit in the MSR (machine state register), with a second bit provided to allow the OS to run with a different endianness. Accesses to the "inverted page table" (a hash table that functions as a TLB with off chip storage) are always done in big endian mode. The processor starts in big endian mode. In little endian mode, the three lowest order bits of the effective address are exclusive ORed with a three bit value selected by the length of the operand. This is enough to appear fully little endian to normal software. An operating system will see a warped view of the world when it accesses external chips such as video and network hardware. Fixing this warped view requires that the motherboard perform an unconditional 64 bit byte swap on all data entering or leaving the processor. Endianness thus becomes a property of the motherboard. An OS that operates in little endian mode on a big endian motherboard must both swap bytes and undo the exclusive OR when accessing little endian chips. AltiVec operations, despite being 128 bit, are treated as if they were 64 bit. This allows for compatibility with little endian motherboards that were designed prior to AltiVec. An interesting side effect of this implementation is that a program can store a 64 bit value (the longest operand format) to memory while in one endian mode, switch modes, and read back the same 64 bit value without seeing a change of byte order. This will not be the case if the motherboard is switched at the same time. Mercury Systems and Matrox ran the PowerPC in little endian mode. This was done so that PowerPC devices serving as co processors on PCI boards could share data structures with host computers based on x86. Both PCI and x86 are little endian. OS/2 and Windows NT for PowerPC ran the processor in little endian mode while Solaris, AIX and Linux ran in big endian. Some of IBM's embedded PowerPC chips use a per page endianness bit. None of the previous applies to them.

The first implementation of the architecture was the PowerPC 601, released in 1992, based on the RSC, implementing a hybrid of the POWER1 and PowerPC instructions. This allowed the chip to be used by IBM in their existing POWER1 based platforms, although it also meant some slight pain when switching to the 2nd generation "pure" PowerPC designs. Apple continued work on a new line of Macintosh computers based on the chip, and eventually released them as the 601 based Power Macintosh on March 14, 1994. Accelerator cards based on the first generation PowerPC chips were created for the Amiga in anticipation for a move to a possible new Amiga platform designed around the PowerPC. The accelerator cards also included either a Motorola 68040 or 68060 CPU in order to maintain backwards compatibility, as very few apps at the time could run natively on the PPC chips. However, the new machines never materialized, and Commodore subsequently declared bankruptcy. Over a decade later, AmigaOS 4 would be released, which would put the platform permanently on the architecture. OS4 is compatible with those first generation accelerators, as well as several custom motherboards created for a new incarnation of the Amiga platform. IBM also had a full line of PowerPC based desktops built and ready to ship; unfortunately, the operating system that IBM had intended to run on these desktops—Microsoft Windows NT—was not complete by early 1993, when the machines were ready for marketing. Accordingly, and further because IBM had developed animosity toward Microsoft, IBM decided to port OS/2 to the PowerPC in the form of Workplace OS. This new software platform spent three years (1992 to 1995) in development and was canceled with the December 1995 developer release, because of the disappointing launch of the PowerPC 620. For this reason, the IBM PowerPC desktops did not ship, although the reference design (codenamed Sandalbow) based on the PowerPC 601 CPU was released as an RS/6000 model (Bytes April 1994 issue included an extensive article about the Apple and IBM PowerPC desktops). Apple, which also lacked a PowerPC based OS, took a different route. Utilizing the portability platform yielded by the secret Star Trek project, the company ported the essential pieces of their Mac OS operating system to the PowerPC architecture, and further wrote a 68k emulator that could run 68k based applications and the parts of the OS that had not been rewritten. The second generation was "pure" and includes the "low end" PowerPC 603 and "high end" PowerPC 604. The 603 is notable due to its very low cost and power consumption. This was a deliberate design goal on Motorola's part, who used the 603 project to build the basic core for all future generations of PPC chips. Apple tried to use the 603 in a new laptop design but was unable due to the small 8 KB level 1 cache. The 68000 emulator in the Mac OS could not fit in 8 KB and thus slowed the computer drastically. The 603e solved this problem by having a 16 KB L1 cache, which allowed the emulator to run efficiently. In 1993, developers at IBM's Essex Junction, Burlington, Vermont facility started to work on a version of the PowerPC that would support the Intel x86 instruction set directly on the CPU. While this was just one of several concurrent power architecture projects that IBM was working on, this chip began to be known inside IBM and by the media as the PowerPC 615. Profitability concerns and rumors of performance issues in the switching between the x86 and native PowerPC instruction sets resulted in the project being canceled in 1995 after only a limited number of chips were produced for in house testing. Aside the rumors, the switching process took only 5 cycles, or the amount of time needed for the processor to empty its instruction pipeline. Microsoft also aided the processor's demise by refusing to support the PowerPC mode. The first 64 bit implementation is the PowerPC 620, but it appears to have seen little use because Apple didn't want to buy it and because, with its large die area, it was too costly for the embedded market. It was later and slower than promised, and IBM used their own POWER3 design instead, offering no 64 bit "small" version until the late 2002 introduction of the PowerPC 970. The 970 is a 64 bit processor derived from the POWER4 server processor. To create it, the POWER4 core was modified to be backward compatible with 32 bit PowerPC processors, and a vector unit (similar to the AltiVec extensions in Motorola's 74xx series) was added. IBM's RS64 processors are a family of chips implementing the "Amazon" variant of the PowerPC architecture. These processors are used in the RS/6000 and IBM AS/400 computer families; the Amazon architecture includes proprietary extensions used by AS/400. The POWER4 and later POWER processors implement the Amazon architecture and replaced the RS64 chips in the RS/6000 and AS/400 families. IBM developed a separate product line called the "4xx" line focused on the embedded market. These designs included the 401, 403, 405, 440, and 460. In 2004, IBM sold their 4xx product line to Applied Micro Circuits Corporation (AMCC). AMCC continues to develop new high performance products, partly based on IBM's technology, along with technology that was developed within AMCC. These products focus on a variety of applications including networking, wireless, storage, printing/imaging and industrial automation. Numerically, the PowerPC is mostly found in controllers in cars. For the automotive market, Freescale Semiconductor initially offered many variations called the MPC5xx family such as the MPC555, built on a variation of the 601 core called the 8xx and designed in Israel by MSIL (Motorola Silicon Israel Limited). The 601 core is single issue, meaning it can only issue one instruction in a clock cycle. To this they add various bits of custom hardware, to allow for I/O on the one chip. In 2004, the next generation four digit 55xx devices were launched for the automotive market. These use the newer e200 series of PowerPC cores. Networking is another area where embedded PowerPC processors are found in large numbers. MSIL took the QUICC engine from the MC68302 and made the PowerQUICC MPC860. This was a very famous processor used in many Cisco edge routers in the late 1990s. Variants of the PowerQUICC include the MPC850, and the MPC823/MPC823e. All variants include a separate RISC microengine called the CPM that offloads communications processing tasks from the central processor and has functions for DMA. The follow on chip from this family, the MPC8260, has a 603e based core and a different CPM. Honda also uses PowerPC processors for its ASIMO robot. In 2003, BAE Systems Platform Solutions delivered the Vehicle Management Computer for the F 35 fighter jet. This platform consists of dual PowerPCs made by Freescale in a triple redundant setup. Aeronautical Development Establishment tested a high performance digital flight control computer, powered by a quadraplex PowerPC based processor setup on a HAL Tejas Mark 1A in 2024.

Operating systems that work on the PowerPC architecture are generally divided into those that are oriented toward the general purpose PowerPC systems, and those oriented toward the embedded PowerPC systems.