Техас: Несостоявшийся преемник Pentium 4 и закат NetBurst

Tejas was a code name for Intel's microprocessor, which was to be a successor to the latest Pentium 4 with the Prescott core and was sometimes referred to as Pentium V. Analysts attribute these issues to heat and power consumption problems due to Intel's goal of reaching ever higher clock speeds, at the detriment of work done per clock (and therefore performance per clock). This was already the case with Prescott and its mediocre performance increase over Northwood despite higher clock speeds, not to mention heavy competition from Advanced Micro Devices with their Athlon 64. Prescott was supposed to attain >5 GHz speeds with ease, yet this was not possible due to physical limitations such as heat generated and power consumed at ambient temperatures. Tejas went even further ahead with this paradigm, with Intel targeting 10GHz clock speeds by 2011 back in July 2000, this statement being made a few months before the Pentium 4 launched. It was soon enough clear this represented a dead end. This cancellation reflected Intel's intention to focus on dual core chips for the Itanium platform. With respect to desktop processors, Intel's development efforts shifted to the Pentium M microarchitecture (itself a derivative of the P6 microarchitecture last used in the Pentium III) used in the Centrino notebook platform, which offered greatly improved performance per watt compared to Prescott and other NetBurst designs. The result of modernizing the P6 microarchitecture was the Core processor line, and later the Core 2 line, offering Intel's first native dual core products for desktops and laptops while regaining the performance crown back from AMD. This defined the end for the NetBurst architecture, with Core setting the foundation and path for power efficient architectures that followed along the Tick–tock model. Although NetBurst was a dead end for the company, its concepts were later reused and repurposed in Sandy Bridge. To bridge the gap left by Tejas' cancellation in the x86 market, Intel did one last revision to NetBurst, codenamed Cedar Mill (single core) and Presler (dual core).

Tejas and Jayhawk were to make several improvements on the Pentium 4's NetBurst microarchitecture. Tejas was originally to be built on a 90 nm process, later moving to a 65 nm process. The 90 nm version of the processor was reported to have 1 MB L2 cache, while the 65 nm chip would increase the cache to 2 MB. There was also to be a dual core version of Tejas called Cedarmill (or Cedar Mill depending on the source). This Cedarmill should not be confused with the 65 nm Cedar Mill based Pentium 4, which appears to be what the codename was recycled for. The trace cache capacity would likely have been increased, and the number of pipeline stages was increased to between 40 and 50 stages. There would have been an improved version of Hyper Threading, as well as a new version of SSE, which was later backported to the Intel Core 2 series and named SSSE3. Tejas was slated to operate at frequencies of 7 GHz or higher. However, it's likely that Tejas wouldn't have had linear performance scaling, as it would on average have executed fewer instructions per clock cycle due to more pipeline bubbles from branch mispredicts and data cache misses. Also, it would have run hotter as well with a TDP much higher than the Prescott core of Pentium 4. The CPU was cancelled late in its development after it had reached its tapeout phase. a notable increase over single core 90 nm Prescott (Pentium 4 521, 2.8 GHz, 84 W TDP) and higher than 90 nm dual core Smithfield (Pentium D 820, 2.8 GHz, 95 W TDP). In contrast, 65 nm dual core Core 2 Duo processors had a maximum of 65 W TDP (E6850, 3.00 GHz) while being much more efficient with markedly higher performance per clock. However, the existence of engineering samples have been challenged and no source indicates that tape out of Tejas ever existed the sample shown in the AnandTech article Most probably only thermal samples of Tejas were produced.